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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// Revision 1.20 2002/02/06 12:23:09 mohor
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// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
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// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
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//
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//
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Revision 1.19 2002/02/05 13:34:51 mohor
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// Stupid bug that was entered by previous update fixed.
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// Stupid bug that was entered by previous update fixed.
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Line 147... |
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// Instructions
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// Instructions
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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// TAP signals
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// TAP signals
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trst, tck, tdi, TDOData,
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trst_in, tck, tdi, TDOData,
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BypassRegister
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BypassRegister
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);
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);
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Line 192... |
input ShiftDR;
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input ShiftDR;
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input Exit1DR;
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input Exit1DR;
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input UpdateDR;
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input UpdateDR;
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input UpdateDR_q;
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input UpdateDR_q;
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input trst;
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input trst_in;
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input tck;
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input tck;
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input tdi;
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input tdi;
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input BypassRegister;
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input BypassRegister;
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Line 230... |
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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wire trst;
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
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wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
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wire RiscStall_reg; // RISC is stalled by setting the register bit
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wire RiscStall_reg; // RISC is stalled by setting the register bit
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Line 322... |
wire BitCounter_Lt40;
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wire BitCounter_Lt40;
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`endif
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`endif
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assign trst = ~trst_in; // trst_pad_i is active low
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* JTAG_DR: JTAG Data Register *
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* JTAG_DR: JTAG Data Register *
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