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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 42 and 43

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Rev 42 Rev 43
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.23  2002/04/17 11:16:33  mohor
 
// A block for checking possible simulation/synthesis missmatch added.
 
//
// Revision 1.22  2002/03/12 10:31:53  mohor
// Revision 1.22  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
// logic necessery for debugging.
//
//
Line 479... Line 482...
        begin
        begin
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
          $stop;
          $stop;
        end
        end
      else
      else
      if(RegisterScanChain & BitCounter > 45)
      if(RegisterScanChain & BitCounter > 46)
        begin
        begin
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
          $display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
          $stop;
          $stop;
        end
        end
      else
      else

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