| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Intentional error removed.
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//
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// Revision 1.23 2002/04/17 11:16:33 mohor
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// Revision 1.23 2002/04/17 11:16:33 mohor
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// A block for checking possible simulation/synthesis missmatch added.
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// A block for checking possible simulation/synthesis missmatch added.
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//
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//
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// Revision 1.22 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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| Line 809... |
Line 812... |
/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Connecting Registers *
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* Connecting Registers *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
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dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
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.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
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.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
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.Bp(bp_i), .Reset(wb_rst_i),
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.bp(bp_i), .reset(wb_rst_i),
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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.ContinMode(ContinMode), .TraceEnable(TraceEnable),
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.ContinMode(ContinMode), .TraceEnable(TraceEnable),
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.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
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.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
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.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
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.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
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| Line 830... |
Line 833... |
.IQualifValid(IQualifValid),
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.IQualifValid(IQualifValid),
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.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
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`endif
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`endif
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.RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
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.risc_stall(RiscStall_reg), .risc_reset(RiscReset_reg)
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|
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);
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);
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|
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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| Line 880... |
Line 883... |
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
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((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
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`endif
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`endif
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);
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);
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// Calculating crc for input data
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// Calculating crc for input data
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dbg_crc8_d1 crc1 (.Data(tdi), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
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dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
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.CrcOut(CalculatedCrcIn), .Clk(tck));
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.crc_out(CalculatedCrcIn), .clk(tck));
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|
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// Calculating crc for output data
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// Calculating crc for output data
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dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
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dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
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.CrcOut(CalculatedCrcOut), .Clk(tck));
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.crc_out(CalculatedCrcOut), .clk(tck));
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|
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// Generating CrcMatch signal
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// Generating CrcMatch signal
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always @ (posedge tck or posedge trst)
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always @ (posedge tck or posedge trst)
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begin
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begin
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