URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_trace.v] - Diff between revs 17 and 20

Rev 17	Rev 20
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2001/10/19 11:40:01 mohor`
	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
	`// few different cores in a single project.`
	`//`
`// Revision 1.4 2001/09/20 10:11:25 mohor`	`// Revision 1.4 2001/09/20 10:11:25 mohor`
`// Working version. Few bugs fixed, comments added.`	`// Working version. Few bugs fixed, comments added.`
`//`	`//`
`// Revision 1.3 2001/09/19 11:55:13 mohor`	`// Revision 1.3 2001/09/19 11:55:13 mohor`
`// Asynchronous set/reset not used in trace any more.`	`// Asynchronous set/reset not used in trace any more.`
Line 67...	Line 71...
`// Initial release`	`// Initial release`
`//`	`//`
`//`	`//`


	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`
`include "dbg_defines.v"	`include "dbg_defines.v"

`// module Trace`	`// module Trace`
`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,`	`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,`
`Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,`	`Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,`