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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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`include "dbg_timescale.v"
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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// module Trace
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// module Trace
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module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall,
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module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall,
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Mclk, Reset, TraceChain, ContinMode, TraceEnable, RecSelDepend,
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Mclk, Reset, TraceChain, ContinMode, TraceEnable,
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WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
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WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
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BpQualif, LSSQualif, IQualif, QualifOper, RecordPC_Wp, RecordLSEA_Wp,
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BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
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RecordLDATA_Wp, RecordSDATA_Wp, RecordReadSPR_Wp, RecordWriteSPR_Wp,
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RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
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RecordINSTR_Wp, RecordPC_Bp, RecordLSEA_Bp, RecordLDATA_Bp,
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RecordINSTR,
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RecordSDATA_Bp, RecordReadSPR_Bp, RecordWriteSPR_Bp, RecordINSTR_Bp,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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LSSStopValid, IStopValid
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LSSStopValid, IStopValid
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);
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);
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Line 90... |
input ReadBuffer;// Instruction for reading a sample from the Buffer
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input ReadBuffer;// Instruction for reading a sample from the Buffer
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// from registers
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// from registers
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input ContinMode;
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input ContinMode;
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input TraceEnable;
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input TraceEnable;
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input RecSelDepend;
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input [10:0] WpTrigger;
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input [10:0] WpTrigger;
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input BpTrigger;
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input BpTrigger;
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input [3:0] LSSTrigger;
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input [3:0] LSSTrigger;
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input [1:0] ITrigger;
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input [1:0] ITrigger;
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Line 109... |
input BpStop;
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input BpStop;
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input [3:0] LSSStop;
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input [3:0] LSSStop;
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input [1:0] IStop;
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input [1:0] IStop;
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input [1:0] StopOper;
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input [1:0] StopOper;
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input [10:0] RecordPC_Wp;
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input RecordPC;
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input [10:0] RecordLSEA_Wp;
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input RecordLSEA;
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input [10:0] RecordLDATA_Wp;
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input RecordLDATA;
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input [10:0] RecordSDATA_Wp;
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input RecordSDATA;
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input [10:0] RecordReadSPR_Wp;
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input RecordReadSPR;
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input [10:0] RecordWriteSPR_Wp;
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input RecordWriteSPR;
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input [10:0] RecordINSTR_Wp;
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input RecordINSTR;
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input RecordPC_Bp;
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input RecordLSEA_Bp;
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input RecordLDATA_Bp;
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input RecordSDATA_Bp;
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input RecordReadSPR_Bp;
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input RecordWriteSPR_Bp;
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input RecordINSTR_Bp;
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input WpTriggerValid;
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input WpTriggerValid;
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input BpTriggerValid;
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input BpTriggerValid;
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input LSSTriggerValid;
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input LSSTriggerValid;
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input ITriggerValid;
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input ITriggerValid;
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Line 135... |
input IStopValid;
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input IStopValid;
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// end: from registers
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// end: from registers
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output CpuStall; // CPU stall (stalls the RISC)
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output RiscStall; // CPU stall (stalls the RISC)
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output [39:0] TraceChain; // Scan shain from the trace module
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output [39:0] TraceChain; // Scan shain from the trace module
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reg [`TRACECOUNTERWIDTH:0] Counter;
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reg [`TRACECOUNTERWIDTH:0] Counter;
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reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
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reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
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reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
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reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
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reg CpuStall;
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reg RiscStall;
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reg CpuStall_q;
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reg RiscStall_q;
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reg [`OPSELECTWIDTH-1:0] StallCounter;
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reg [`OPSELECTWIDTH-1:0] StallCounter;
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reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
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reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
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reg TriggerLatch;
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reg TriggerLatch;
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Line 255... |
end
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end
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* CpuStall, counter and pointers generation *
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* RiscStall, counter and pointers generation *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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reg BufferFullDetected;
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reg BufferFullDetected;
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reg [`OPSELECTIONCOUNTER-1:0] RecEnable;
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wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
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wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
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wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
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wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
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wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
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wire IncrementCounter = CpuStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
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wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
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wire IncrementPointer = CpuStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
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wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
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wire WriteSample = IncrementPointer;
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wire WriteSample = IncrementPointer;
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wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
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wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
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wire CounterEn = IncrementCounter ^ Decrement;
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wire CounterEn = IncrementCounter ^ Decrement;
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Line 283... |
always @(posedge Mclk)
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always @(posedge Mclk)
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begin
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begin
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Qualifier_mclk<=#Tp Qualifier;
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Qualifier_mclk<=#Tp Qualifier;
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BufferFull_q<=#Tp BufferFull;
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BufferFull_q<=#Tp BufferFull;
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BufferFull_2q<=#Tp BufferFull_q;
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BufferFull_2q<=#Tp BufferFull_q;
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CpuStall_q <=#Tp CpuStall;
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RiscStall_q <=#Tp RiscStall;
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end
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end
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wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
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wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
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Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
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Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
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Line 351... |
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always @(posedge Mclk or posedge AsyncSetCpuStall)
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always @(posedge Mclk or posedge AsyncSetCpuStall)
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begin
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begin
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if(AsyncSetCpuStall)
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if(AsyncSetCpuStall)
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CpuStall<=#Tp 1;
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RiscStall<=#Tp 1;
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else
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else
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if(SyncSetCpuStall)
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if(SyncSetCpuStall)
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CpuStall<=#Tp 1;
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RiscStall<=#Tp 1;
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else
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else
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if(ResetCpuStall)
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if(ResetCpuStall)
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CpuStall<=#Tp 0;
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RiscStall<=#Tp 0;
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end
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end
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always @(posedge Mclk)
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always @(posedge Mclk)
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begin
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begin
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if(ResetStallCounter)
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if(ResetStallCounter)
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StallCounter<=#Tp 0;
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StallCounter<=#Tp 0;
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else
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else
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if(CpuStall_q & (~BufferFull | ContinMode))
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if(RiscStall_q & (~BufferFull | ContinMode))
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StallCounter<=#Tp StallCounter+1;
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StallCounter<=#Tp StallCounter+1;
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end
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end
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assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
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assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Selecting which parts are going to be recorded as part of the sample *
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* Selecting which parts are going to be recorded as part of the sample *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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always @(posedge Mclk or posedge Reset)
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assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
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begin
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if(Reset)
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RecEnable<=#Tp 0;
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else
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if(CpuStall)
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begin
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RecEnable<=#Tp {1'b0, RecordINSTR_Wp[0], RecordWriteSPR_Wp[0], RecordReadSPR_Wp[0], RecordSDATA_Wp[0], RecordLDATA_Wp[0], RecordLSEA_Wp[0], RecordPC_Wp[0]} & {`OPSELECTIONCOUNTER{Wp[0]}} |
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{1'b0, RecordINSTR_Wp[1], RecordWriteSPR_Wp[1], RecordReadSPR_Wp[1], RecordSDATA_Wp[1], RecordLDATA_Wp[1], RecordLSEA_Wp[1], RecordPC_Wp[1]} & {`OPSELECTIONCOUNTER{Wp[1]}} |
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{1'b0, RecordINSTR_Wp[2], RecordWriteSPR_Wp[2], RecordReadSPR_Wp[2], RecordSDATA_Wp[2], RecordLDATA_Wp[2], RecordLSEA_Wp[2], RecordPC_Wp[2]} & {`OPSELECTIONCOUNTER{Wp[2]}} |
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{1'b0, RecordINSTR_Wp[3], RecordWriteSPR_Wp[3], RecordReadSPR_Wp[3], RecordSDATA_Wp[3], RecordLDATA_Wp[3], RecordLSEA_Wp[3], RecordPC_Wp[3]} & {`OPSELECTIONCOUNTER{Wp[3]}} |
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{1'b0, RecordINSTR_Wp[4], RecordWriteSPR_Wp[4], RecordReadSPR_Wp[4], RecordSDATA_Wp[4], RecordLDATA_Wp[4], RecordLSEA_Wp[4], RecordPC_Wp[4]} & {`OPSELECTIONCOUNTER{Wp[4]}} |
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{1'b0, RecordINSTR_Wp[5], RecordWriteSPR_Wp[5], RecordReadSPR_Wp[5], RecordSDATA_Wp[5], RecordLDATA_Wp[5], RecordLSEA_Wp[5], RecordPC_Wp[5]} & {`OPSELECTIONCOUNTER{Wp[5]}} |
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{1'b0, RecordINSTR_Wp[6], RecordWriteSPR_Wp[6], RecordReadSPR_Wp[6], RecordSDATA_Wp[6], RecordLDATA_Wp[6], RecordLSEA_Wp[6], RecordPC_Wp[6]} & {`OPSELECTIONCOUNTER{Wp[6]}} |
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{1'b0, RecordINSTR_Wp[7], RecordWriteSPR_Wp[7], RecordReadSPR_Wp[7], RecordSDATA_Wp[7], RecordLDATA_Wp[7], RecordLSEA_Wp[7], RecordPC_Wp[7]} & {`OPSELECTIONCOUNTER{Wp[7]}} |
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{1'b0, RecordINSTR_Wp[8], RecordWriteSPR_Wp[8], RecordReadSPR_Wp[8], RecordSDATA_Wp[8], RecordLDATA_Wp[8], RecordLSEA_Wp[8], RecordPC_Wp[8]} & {`OPSELECTIONCOUNTER{Wp[8]}} |
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{1'b0, RecordINSTR_Wp[9], RecordWriteSPR_Wp[9], RecordReadSPR_Wp[9], RecordSDATA_Wp[9], RecordLDATA_Wp[9], RecordLSEA_Wp[9], RecordPC_Wp[9]} & {`OPSELECTIONCOUNTER{Wp[9]}} |
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{1'b0, RecordINSTR_Wp[10], RecordWriteSPR_Wp[10], RecordReadSPR_Wp[10], RecordSDATA_Wp[10], RecordLDATA_Wp[10], RecordLSEA_Wp[10], RecordPC_Wp[10]}& {`OPSELECTIONCOUNTER{Wp[10]}} |
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{1'b0, RecordINSTR_Bp, RecordWriteSPR_Bp, RecordReadSPR_Bp, RecordSDATA_Bp, RecordLDATA_Bp, RecordLSEA_Bp, RecordPC_Bp} & {`OPSELECTIONCOUNTER{Bp}};
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end
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end
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endmodule // Trace
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endmodule // Trace
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