| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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| Line 62... |
Line 65... |
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`include "dbg_timescale.v"
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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// module Trace
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// module Trace
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module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall,
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module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
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Mclk, Reset, TraceChain, ContinMode, TraceEnable,
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Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
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WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
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WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
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BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
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BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
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RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
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RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
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RecordINSTR,
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RecordINSTR,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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| Line 89... |
Line 92... |
input Reset; // Reset
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input Reset; // Reset
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input ReadBuffer;// Instruction for reading a sample from the Buffer
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input ReadBuffer;// Instruction for reading a sample from the Buffer
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// from registers
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// from registers
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input ContinMode;
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input ContinMode;
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input TraceEnable;
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input TraceEnable_reg;
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input [10:0] WpTrigger;
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input [10:0] WpTrigger;
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input BpTrigger;
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input BpTrigger;
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input [3:0] LSSTrigger;
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input [3:0] LSSTrigger;
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input [1:0] ITrigger;
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input [1:0] ITrigger;
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| Line 135... |
Line 138... |
input IStopValid;
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input IStopValid;
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// end: from registers
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// end: from registers
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output RiscStall; // CPU stall (stalls the RISC)
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output RiscStall_O; // CPU stall (stalls the RISC)
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output [39:0] TraceChain; // Scan shain from the trace module
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output [39:0] TraceChain; // Scan shain from the trace module
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reg TraceEnable_d;
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reg TraceEnable;
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reg [`TRACECOUNTERWIDTH:0] Counter;
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reg [`TRACECOUNTERWIDTH:0] Counter;
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reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
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reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
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reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
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reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
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reg RiscStall;
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reg RiscStall;
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| Line 242... |
Line 249... |
/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Generation of the TriggerLatch *
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* Generation of the TriggerLatch *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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wire Reset_TriggerLatch = Reset | TriggerLatch & ~TraceEnable;
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always @(posedge Mclk or posedge Reset)
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always @(posedge Mclk or posedge Reset_TriggerLatch)
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begin
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begin
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if(Reset_TriggerLatch)
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if(Reset)
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TriggerLatch<=#Tp 0;
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else
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if(TriggerLatch & ~TraceEnable)
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TriggerLatch<=#Tp 0;
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TriggerLatch<=#Tp 0;
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else
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else
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if(Trigger)
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if(Trigger)
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TriggerLatch<=#Tp 1;
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TriggerLatch<=#Tp 1;
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end
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end
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/**********************************************************************************
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* *
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* TraceEnable Synchronization *
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* *
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**********************************************************************************/
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always @(posedge Mclk or posedge Reset)
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begin
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if(Reset)
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begin
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TraceEnable_d<=#Tp 0;
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TraceEnable<=#Tp 0;
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end
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else
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begin
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TraceEnable_d<=#Tp TraceEnable_reg;
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TraceEnable<=#Tp TraceEnable_d;
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end
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end
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* RiscStall, counter and pointers generation *
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* RiscStall, counter and pointers generation *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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| Line 271... |
Line 304... |
wire WriteSample = IncrementPointer;
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wire WriteSample = IncrementPointer;
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wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
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wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
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wire CounterEn = IncrementCounter ^ Decrement;
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wire CounterEn = IncrementCounter ^ Decrement;
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wire ResetCpuStall;
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wire SyncResetCpuStall;
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wire ResetStallCounter;
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wire ResetStallCounter;
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reg BufferFull_q;
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reg BufferFull_q;
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reg BufferFull_2q;
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reg BufferFull_2q;
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reg Qualifier_mclk;
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reg Qualifier_mclk;
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| Line 283... |
Line 316... |
always @(posedge Mclk)
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always @(posedge Mclk)
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begin
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begin
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Qualifier_mclk<=#Tp Qualifier;
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Qualifier_mclk<=#Tp Qualifier;
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BufferFull_q<=#Tp BufferFull;
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BufferFull_q<=#Tp BufferFull;
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BufferFull_2q<=#Tp BufferFull_q;
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BufferFull_2q<=#Tp BufferFull_q;
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RiscStall_q <=#Tp RiscStall;
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RiscStall_q <=#Tp RiscStall_O;
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end
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end
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wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
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wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch |
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Qualifier_mclk & Trigger & ~TriggerLatch |
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Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
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Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
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wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
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//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
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wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
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Qualifier_mclk & TriggerLatch &
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(
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(
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
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(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
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);
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);
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assign ResetCpuStall = (
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assign SyncResetCpuStall = (
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
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(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
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(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
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( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
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) | Reset;
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);
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assign RiscStall_O = FirstCpuStall | RiscStall;
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always @(posedge Mclk or posedge Reset)
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always @(posedge Mclk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 321... |
Line 360... |
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always @(posedge Mclk or posedge Reset)
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always @(posedge Mclk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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begin
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WritePointer<=#Tp 0;
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WritePointer<=#Tp 0;
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ReadPointer<=#Tp 0;
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end
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else
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else
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begin
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if(IncrementPointer)
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if(IncrementPointer)
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WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
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WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
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// else igor !!! Probably else is missing here. Check it.
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end
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always @(posedge Mclk or posedge Reset)
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begin
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if(Reset)
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ReadPointer<=#Tp 0;
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else
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if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
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if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
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ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
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ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
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else
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else
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if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
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if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
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ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
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ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
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end
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end
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end
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always @(posedge Mclk)
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always @(posedge Mclk)
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begin
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begin
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if(~TraceEnable)
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if(~TraceEnable)
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BufferFullDetected<=#Tp 0;
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BufferFullDetected<=#Tp 0;
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| Line 348... |
Line 388... |
if(ContinMode & BufferFull)
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if(ContinMode & BufferFull)
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BufferFullDetected<=#Tp 1;
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BufferFullDetected<=#Tp 1;
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end
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end
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always @(posedge Mclk or posedge AsyncSetCpuStall)
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always @(posedge Mclk or posedge Reset)
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begin
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begin
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if(AsyncSetCpuStall)
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if(Reset)
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RiscStall<=#Tp 1;
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RiscStall<=#Tp 0;
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else
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if(SyncResetCpuStall)
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RiscStall<=#Tp 0;
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else
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else
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if(SyncSetCpuStall)
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if(SyncSetCpuStall)
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RiscStall<=#Tp 1;
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RiscStall<=#Tp 1;
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else
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if(ResetCpuStall)
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RiscStall<=#Tp 0;
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end
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end
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always @(posedge Mclk)
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always @(posedge Mclk)
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begin
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begin
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