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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/19 11:55:13 mohor
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// Asynchronous set/reset not used in trace any more.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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input Mclk; // Master clock (RISC clock)
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input Mclk; // Master clock (RISC clock)
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input Reset; // Reset
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input Reset; // Reset
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input ReadBuffer;// Instruction for reading a sample from the Buffer
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input ReadBuffer;// Instruction for reading a sample from the Buffer
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// from registers
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// from registers
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input ContinMode;
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input ContinMode; // Continous mode of the trace
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input TraceEnable_reg;
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input TraceEnable_reg; // Trace is enabled (enabled by writing a bit in the register)
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input [10:0] WpTrigger;
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input [10:0] WpTrigger; // Signals that come from registers to set the trigger
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input BpTrigger;
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input BpTrigger; // Signals that come from registers to set the trigger
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input [3:0] LSSTrigger;
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input [3:0] LSSTrigger; // Signals that come from registers to set the trigger
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input [1:0] ITrigger;
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input [1:0] ITrigger; // Signals that come from registers to set the trigger
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input [1:0] TriggerOper;
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input [1:0] TriggerOper; // Signals that come from registers to set the trigger
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input [10:0] WpQualif;
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input [10:0] WpQualif; // Signals that come from registers to set the qualifier
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input BpQualif;
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input BpQualif; // Signals that come from registers to set the qualifier
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input [3:0] LSSQualif;
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input [3:0] LSSQualif; // Signals that come from registers to set the qualifier
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input [1:0] IQualif;
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input [1:0] IQualif; // Signals that come from registers to set the qualifier
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input [1:0] QualifOper;
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input [1:0] QualifOper; // Signals that come from registers to set the qualifier
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input [10:0] WpStop;
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input [10:0] WpStop; // Signals that come from registers to set the stop condition
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input BpStop;
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input BpStop; // Signals that come from registers to set the stop condition
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input [3:0] LSSStop;
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input [3:0] LSSStop; // Signals that come from registers to set the stop condition
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input [1:0] IStop;
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input [1:0] IStop; // Signals that come from registers to set the stop condition
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input [1:0] StopOper;
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input [1:0] StopOper; // Signals that come from registers to set the stop condition
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input RecordPC;
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input RecordPC; // Signals that come from registers for defining the sample for recording
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input RecordLSEA;
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input RecordLSEA; // Signals that come from registers for defining the sample for recording
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input RecordLDATA;
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input RecordLDATA; // Signals that come from registers for defining the sample for recording
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input RecordSDATA;
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input RecordSDATA; // Signals that come from registers for defining the sample for recording
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input RecordReadSPR;
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input RecordReadSPR; // Signals that come from registers for defining the sample for recording
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input RecordWriteSPR;
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input RecordWriteSPR; // Signals that come from registers for defining the sample for recording
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input RecordINSTR;
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input RecordINSTR; // Signals that come from registers for defining the sample for recording
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input WpTriggerValid;
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input WpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input BpTriggerValid;
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input BpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input LSSTriggerValid;
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input LSSTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input ITriggerValid;
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input ITriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
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input WpQualifValid;
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input WpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input BpQualifValid;
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input BpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input LSSQualifValid;
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input LSSQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input IQualifValid;
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input IQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
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input WpStopValid;
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input WpStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input BpStopValid;
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input BpStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input LSSStopValid;
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input LSSStopValid; // Signals that come from registers and indicate which stop conditions are valid
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input IStopValid;
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input IStopValid; // Signals that come from registers and indicate which stop conditions are valid
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// end: from registers
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// end: from registers
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
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output RiscStall_O; // CPU stall (stalls the RISC)
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output RiscStall_O; // CPU stall (stalls the RISC)
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
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assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
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endmodule // Trace
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endmodule
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No newline at end of file
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No newline at end of file
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