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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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//
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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Line 60... |
// Top module
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// Top module
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module tap_top(
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module tap_top(
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// JTAG pins
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// JTAG pins
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
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tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
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// RISC signals
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// TAP states
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risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
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ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
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bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
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// Instructions
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// WISHBONE common signals
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IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
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wb_rst_i, wb_clk_i,
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// TDO from dbg module
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// WISHBONE master interface
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TDOData_dbg, BypassRegister
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wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
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wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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// JTAG pins
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// JTAG pins
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Line 80... |
input trst_pad_i; // JTAG test reset pad
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input trst_pad_i; // JTAG test reset pad
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input tdi_pad_i; // JTAG test data input pad
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input tdi_pad_i; // JTAG test data input pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_pad_o; // JTAG test data output pad
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output tdo_padoen_o; // Output enable for JTAG test data output pad
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output tdo_padoen_o; // Output enable for JTAG test data output pad
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// TAP states
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output ShiftDR;
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output Exit1DR;
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output UpdateDR;
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output UpdateDR_q;
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// RISC signals
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// Instructions
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input risc_clk_i; // Master clock (RISC clock)
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output IDCODESelected;
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input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
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output CHAIN_SELECTSelected;
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input [10:0] wp_i; // Watchpoint inputs
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output DEBUGSelected;
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input bp_i; // Breakpoint input
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input [3:0] lsstatus_i; // Load/store status inputs
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input [1:0] istatus_i; // Instruction status inputs
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output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
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output [31:0] risc_data_o; // RISC data output (data read from risc registers)
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output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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output risc_stall_o; // Stalls the RISC
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output reset_o; // Resets the RISC
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// WISHBONE common signals
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input wb_rst_i; // WISHBONE reset
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input wb_clk_i; // WISHBONE clock
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// WISHBONE master interface
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_stb_o;
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output [3:0] wb_sel_o;
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output wb_we_o;
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input wb_ack_i;
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output wb_cab_o;
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input wb_err_i;
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input TDOData_dbg;
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output BypassRegister;
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reg tdo_pad_o;
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reg tdo_pad_o;
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// TAP states
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// TAP states
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reg TestLogicReset;
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reg TestLogicReset;
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Line 134... |
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wire trst; // trst is active high while trst_pad_i is active low
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wire trst; // trst is active high while trst_pad_i is active low
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wire tck;
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wire tck;
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wire TMS;
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wire TMS;
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wire tdi;
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wire tdi;
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wire TDOData;
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wire RiscDebugScanChain;
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wire RiscDebugScanChain;
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wire WishboneScanChain;
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wire WishboneScanChain;
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wire RegisterScanChain;
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wire RegisterScanChain;
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wire bs_chain_o;
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wire bs_chain_o;
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Line 538... |
* Multiplexing TDO data *
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* Multiplexing TDO data *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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// This multiplexer can be expanded with number of user registers
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// This multiplexer can be expanded with number of user registers
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always @ (LatchedJTAG_IR or TDOInstruction or TDOData or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)
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always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_o or ShiftIR or Exit1IR)
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begin
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begin
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if(ShiftIR | Exit1IR)
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if(ShiftIR | Exit1IR)
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tdo_pad_o <=#Tp TDOInstruction;
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tdo_pad_o <=#Tp TDOInstruction;
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else
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else
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begin
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begin
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case(LatchedJTAG_IR)
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case(LatchedJTAG_IR)
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`IDCODE: tdo_pad_o <=#Tp TDOData; // Reading ID code
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`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
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`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData; // Selecting the chain
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`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
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`DEBUG: tdo_pad_o <=#Tp TDOData; // Debug
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`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
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`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_o; // Sampling/Preloading
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`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_o; // Sampling/Preloading
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`EXTEST: tdo_pad_o <=#Tp bs_chain_o; // External test
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`EXTEST: tdo_pad_o <=#Tp bs_chain_o; // External test
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default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
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default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
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endcase
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endcase
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end
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end
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Line 564... |
* *
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* *
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* End: Multiplexing TDO data *
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* End: Multiplexing TDO data *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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// Connecting dbg_top module
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dbg_top i_dbg_top (
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// RISC signals
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.risc_clk_i(risc_clk_i), .risc_addr_o(risc_addr_o), .risc_data_i(risc_data_i),
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.risc_data_o(risc_data_o), .wp_i(wp_i), .bp_i(bp_i),
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.opselect_o(opselect_o), .lsstatus_i(lsstatus_i), .istatus_i(istatus_i),
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.risc_stall_o(risc_stall_o), .reset_o(reset_o),
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// WISHBONE common signals
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.wb_rst_i(wb_rst_i), .wb_clk_i(wb_clk_i),
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// WISHBONE master interface
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.wb_adr_o(wb_adr_o), .wb_dat_o(wb_dat_o), .wb_dat_i(wb_dat_i),
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.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_sel_o(wb_sel_o),
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.wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), .wb_cab_o(wb_cab_o),
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.wb_err_i(wb_err_i),
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR),
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.UpdateDR_q(UpdateDR_q),
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// Instructions
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.IDCODESelected(IDCODESelected),
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.CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected),
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// TAP signals
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.trst(trst), .tck(tck), .tdi(tdi),
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.TDOData(TDOData),
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.BypassRegister(BypassRegister)
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);
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// Connecting bender_jtag module
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jtag_chain i_jtag_chain (
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.capture_dr_i(CaptureDR), .shift_dr_i(ShiftDR),
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.update_dr_i(UpdateDR), .extest_selected_i(EXTESTSelected),
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.bs_chain_i(tdi), .bs_chain_o(bs_chain_o)
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);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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