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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// cpu_behavioral.v ////
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//// cpu_behavioral.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2004/01/22 11:07:28 mohor
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// test stall_test added.
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//
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// Revision 1.2 2004/01/17 18:01:31 mohor
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// Revision 1.2 2004/01/17 18:01:31 mohor
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// New version.
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// New version.
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//
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//
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// Revision 1.1 2004/01/17 17:01:25 mohor
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// Revision 1.1 2004/01/17 17:01:25 mohor
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// Almost finished.
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// Almost finished.
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cpu_addr_i,
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cpu_addr_i,
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cpu_data_o,
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cpu_data_o,
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cpu_data_i,
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cpu_data_i,
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cpu_bp_o,
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cpu_bp_o,
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cpu_stall_i,
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cpu_stall_i,
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cpu_stall_all_i,
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cpu_stb_i,
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cpu_stb_i,
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cpu_sel_i,
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cpu_we_i,
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cpu_we_i,
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cpu_ack_o,
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cpu_ack_o,
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cpu_rst_o
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cpu_rst_o
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);
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);
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input [31:0] cpu_addr_i;
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input [31:0] cpu_addr_i;
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output [31:0] cpu_data_o;
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output [31:0] cpu_data_o;
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input [31:0] cpu_data_i;
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input [31:0] cpu_data_i;
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output cpu_bp_o;
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output cpu_bp_o;
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input cpu_stall_i;
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input cpu_stall_i;
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input cpu_stall_all_i;
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input cpu_stb_i;
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input cpu_stb_i;
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input [`CPU_NUM -1:0] cpu_sel_i;
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input cpu_we_i;
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input cpu_we_i;
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output cpu_ack_o;
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output cpu_ack_o;
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output cpu_rst_o;
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output cpu_rst_o;
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reg cpu_clk_o;
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reg cpu_clk_o;
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reg [31:0] cpu_data_o;
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reg [31:0] cpu_data_o;
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reg cpu_bp_o;
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reg cpu_bp_o;
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reg cpu_ack_o;
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reg cpu_ack_q;
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wire cpu_ack;
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initial
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initial
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begin
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begin
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cpu_clk_o = 1'b0;
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cpu_clk_o = 1'b0;
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forever #5 cpu_clk_o = ~cpu_clk_o;
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forever #5 cpu_clk_o = ~cpu_clk_o;
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end
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end
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initial
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initial
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begin
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begin
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cpu_bp_o = 1'b0;
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cpu_bp_o = 1'b0;
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end
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end
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assign #200 cpu_ack_o = cpu_stall_i & cpu_stb_i;
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assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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begin
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if (cpu_rst_i)
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begin
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cpu_ack_o <= #1 1'b0;
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cpu_ack_q <= #1 1'b0;
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end
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else
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begin
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cpu_ack_o <= #1 cpu_ack;
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cpu_ack_q <= #1 cpu_ack_o;
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end
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end
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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always @ (posedge cpu_clk_o or posedge cpu_rst_i)
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begin
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begin
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if (cpu_rst_i)
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if (cpu_rst_i)
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cpu_data_o <= #1 32'h11111111;
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cpu_data_o <= #1 32'h12345678;
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else if ((cpu_addr_i == 32'h32323232) & cpu_we_i & cpu_ack_o)
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else if (cpu_ack_o && (!cpu_ack_q))
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cpu_data_o <= #1 cpu_data_i + 1'd1;
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cpu_data_o <= #1 cpu_data_o + 32'h11111111;
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else if ((cpu_addr_i == 32'h08080808) & cpu_we_i & cpu_ack_o)
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cpu_data_o <= #1 cpu_data_i + 2'd2;
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end
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end
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