| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2004/01/22 13:58:51 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.35 2004/01/22 11:07:28 mohor
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// Revision 1.35 2004/01/22 11:07:28 mohor
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// test stall_test added.
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// test stall_test added.
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//
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//
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// Revision 1.34 2004/01/20 14:24:08 mohor
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// Revision 1.34 2004/01/20 14:24:08 mohor
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// Define name changed.
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// Define name changed.
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| Line 411... |
Line 414... |
forever #5 wb_clk_i = ~wb_clk_i;
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forever #5 wb_clk_i = ~wb_clk_i;
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end
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end
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always @ (posedge test_enabled)
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always @ (posedge test_enabled)
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begin
|
begin
|
|
|
$display("//////////////////////////////////////////////////////////////////");
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$display("//////////////////////////////////////////////////////////////////");
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$display("// //");
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$display("// //");
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$display("// (%0t) dbg_tb starting //", $time);
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$display("// (%0t) dbg_tb starting //", $time);
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$display("// //");
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$display("// //");
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$display("//////////////////////////////////////////////////////////////////");
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$display("//////////////////////////////////////////////////////////////////");
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$display("TEST: DBG_TEST");
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initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000
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initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000
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reset_tap;
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reset_tap;
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#500;
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#500;
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| Line 573... |
Line 578... |
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#5000 gen_clk(1); // One extra TCLK for debugging purposes
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#5000 gen_clk(1); // One extra TCLK for debugging purposes
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$display("STATUS: passed");
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$display("\n\nSimulation end.");
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$display("\n\nSimulation end.");
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#1000 $stop;
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#1000 $stop;
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|
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end
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end
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