| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.38 2004/01/30 10:24:02 mohor
|
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
|
// turned on.
|
|
//
|
// Revision 1.37 2004/01/25 14:10:25 mohor
|
// Revision 1.37 2004/01/25 14:10:25 mohor
|
// Display for VATS added.
|
// Display for VATS added.
|
//
|
//
|
// Revision 1.36 2004/01/22 13:58:51 mohor
|
// Revision 1.36 2004/01/22 13:58:51 mohor
|
// Port signals are all set to zero after reset.
|
// Port signals are all set to zero after reset.
|
| Line 760... |
Line 764... |
end
|
end
|
|
|
tdi_pad_i<=#1 instr[i]; // last shift
|
tdi_pad_i<=#1 instr[i]; // last shift
|
tms_pad_i<=#1 1; // going out of shiftIR
|
tms_pad_i<=#1 1; // going out of shiftIR
|
gen_clk(1);
|
gen_clk(1);
|
tdi_pad_i<=#1 'hz; // tri-state
|
tdi_pad_i<=#1 1'hz; // tri-state
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // we are in RunTestIdle
|
gen_clk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
| Line 787... |
Line 791... |
tms_pad_i<=#1 1; // going out of shiftIR
|
tms_pad_i<=#1 1; // going out of shiftIR
|
gen_clk(1);
|
gen_clk(1);
|
|
|
code = in_data_le;
|
code = in_data_le;
|
|
|
tdi_pad_i<=#1 'hz; // tri-state
|
tdi_pad_i<=#1 1'hz; // tri-state
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // we are in RunTestIdle
|
gen_clk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
| Line 835... |
Line 839... |
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tdi_pad_i<=#1 'hz; // tri-state
|
tdi_pad_i<=#1 1'hz; // tri-state
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
|
|
| Line 990... |
Line 994... |
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
| Line 1336... |
Line 1340... |
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
