| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.39 2004/03/15 16:17:07 igorm
|
|
// 'hz changed to 1'hz because Icarus complains.
|
|
//
|
// Revision 1.38 2004/01/30 10:24:02 mohor
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// Revision 1.38 2004/01/30 10:24:02 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
// turned on.
|
// turned on.
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//
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//
|
// Revision 1.37 2004/01/25 14:10:25 mohor
|
// Revision 1.37 2004/01/25 14:10:25 mohor
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| Line 259... |
Line 262... |
reg [31:0] id;
|
reg [31:0] id;
|
|
|
wire crc_match_in;
|
wire crc_match_in;
|
reg [31:0] crc_in;
|
reg [31:0] crc_in;
|
reg [31:0] crc_out;
|
reg [31:0] crc_out;
|
|
reg [`DBG_TOP_STATUS_LEN -1:0] status;
|
|
|
wire tdo;
|
wire tdo;
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|
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
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|
|
| Line 460... |
Line 463... |
`endif
|
`endif
|
|
|
// Testing read and write to internal registers
|
// Testing read and write to internal registers
|
#10000;
|
#10000;
|
|
|
set_instruction(`IDCODE);
|
id_test;
|
read_id_code(id);
|
|
|
|
$display("\tRead ID = 0x%0x", id);
|
|
$display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
|
|
|
|
set_instruction(`DEBUG);
|
set_instruction(`DEBUG);
|
#10000;
|
#10000;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#100000;
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef WISHBONE_SUPPORTED
|
chain_select(`WISHBONE_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
|
module_select(`WISHBONE_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
|
|
#10000;
|
#10000;
|
|
debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
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|
|
|
#100000;
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|
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
|
//
|
//
|
| Line 537... |
Line 550... |
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
|
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
|
`endif // WISHBONE_SUPPORTED
|
`endif // WISHBONE_SUPPORTED
|
|
|
`ifdef CPU_SUPPORTED
|
`ifdef CPU_SUPPORTED
|
#10000;
|
#10000;
|
chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
|
module_select(`CPU_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
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|
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// Select cpu0
|
// Select cpu0
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| Line 630... |
Line 643... |
gen_clk(1);
|
gen_clk(1);
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#1 check_stall(1); // set?
|
#1 check_stall(1); // set?
|
|
|
// Unstall with register
|
// Unstall with register
|
set_instruction(`DEBUG);
|
set_instruction(`DEBUG);
|
chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
|
module_select(`CPU_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
#1 check_stall(1); // set?
|
#1 check_stall(1); // set?
|
debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
|
debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
|
#1 check_stall(1); // set?
|
#1 check_stall(1); // set?
|
debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
#1 check_stall(0); // reset?
|
#1 check_stall(0); // reset?
|
| Line 693... |
Line 706... |
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
task id_test;
|
|
begin
|
|
test_text = "id_test";
|
|
$display("\n\n(%0t) TEST: id_test", $time);
|
|
|
|
set_instruction(`IDCODE);
|
|
read_id_code(id);
|
|
|
|
`ifdef MORE_DBG_INFO
|
|
$display("\tRead ID = 0x%0x", id);
|
|
$display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
|
|
`endif
|
|
|
|
if (id==`IDCODE_VALUE)
|
|
$display("(%0t) STATUS: passed\n", $time);
|
|
else
|
|
$display("(%0t) STATUS: failed (Read ID = 0x%0x, Expected ID = 0x%0x\n", $time, id, `IDCODE_VALUE);
|
|
end
|
|
endtask // id_test
|
|
|
|
|
// Generation of the TCLK signal
|
// Generation of the TCLK signal
|
task gen_clk;
|
task gen_clk;
|
input [7:0] num;
|
input [7:0] num;
|
integer i;
|
integer i;
|
| Line 736... |
Line 769... |
input [3:0] instr;
|
input [3:0] instr;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
case (instr)
|
case (instr)
|
|
`ifdef MORE_DBG_INFO
|
`EXTEST : $display("(%0t) Task set_instruction (EXTEST)", $time);
|
`EXTEST : $display("(%0t) Task set_instruction (EXTEST)", $time);
|
`SAMPLE_PRELOAD : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
|
`SAMPLE_PRELOAD : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
|
`IDCODE : $display("(%0t) Task set_instruction (IDCODE)", $time);
|
`IDCODE : $display("(%0t) Task set_instruction (IDCODE)", $time);
|
`DEBUG : $display("(%0t) Task set_instruction (DEBUG)", $time);
|
`DEBUG : $display("(%0t) Task set_instruction (DEBUG)", $time);
|
`MBIST : $display("(%0t) Task set_instruction (MBIST)", $time);
|
`MBIST : $display("(%0t) Task set_instruction (MBIST)", $time);
|
`BYPASS : $display("(%0t) Task set_instruction (BYPASS)", $time);
|
`BYPASS : $display("(%0t) Task set_instruction (BYPASS)", $time);
|
|
`else
|
|
`EXTEST : ;
|
|
`SAMPLE_PRELOAD : ;
|
|
`IDCODE : ;
|
|
`DEBUG : ;
|
|
`MBIST : ;
|
|
`BYPASS : ;
|
|
`endif
|
default
|
default
|
begin
|
begin
|
$display("(%0t) Task set_instruction (Unsupported instruction !!!)", $time);
|
$display("(*E) (%0t) Task set_instruction: Unsupported instruction !!!", $time);
|
$display("\tERROR: Unsupported instruction !!!", $time);
|
|
$stop;
|
$stop;
|
end
|
end
|
endcase
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endcase
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|
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tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
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| Line 777... |
Line 818... |
// Reads the ID code
|
// Reads the ID code
|
task read_id_code;
|
task read_id_code;
|
output [31:0] code;
|
output [31:0] code;
|
reg [31:0] code;
|
reg [31:0] code;
|
begin
|
begin
|
|
`ifdef MORE_DBG_INFO
|
$display("(%0t) Task read_id_code", $time);
|
$display("(%0t) Task read_id_code", $time);
|
|
`endif
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
| Line 799... |
Line 842... |
gen_clk(1); // we are in RunTestIdle
|
gen_clk(1); // we are in RunTestIdle
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
// sets the selected scan chain and goes to the RunTestIdle state
|
// sets the selected module and goes to the RunTestIdle state
|
task chain_select;
|
task module_select;
|
input [3:0] data;
|
input [`MODULE_ID_LENGTH -1:0] data;
|
input gen_crc_err;
|
input gen_crc_err;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
case (data)
|
case (data)
|
`CPU_DEBUG_CHAIN : $display("(%0t) Task chain_select (CPU_DEBUG_CHAIN, gen_crc_err=%0d)", $time, gen_crc_err);
|
`CPU_DEBUG_MODULE : $display("(%0t) Task module_select (CPU_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
|
`WISHBONE_DEBUG_CHAIN : $display("(%0t) Task chain_select (WISHBONE_DEBUG_CHAIN, gen_crc_err=%0d)", $time, gen_crc_err);
|
`WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
|
default : $display("(%0t) Task chain_select (ERROR!!! Unknown chain selected)", $time);
|
default : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
|
endcase
|
endcase
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1'b1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 1'b0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
status = {`DBG_TOP_STATUS_LEN{1'b0}}; // Initialize status to all 0's
|
tdi_pad_i<=#1 1'b1; // chain_select bit
|
crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
|
tdi_pad_i<=#1 1'b1; // module_select bit
|
calculate_crc(1'b1);
|
calculate_crc(1'b1);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
|
for(i=`MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
|
begin
|
begin
|
tdi_pad_i<=#1 data[i];
|
tdi_pad_i<=#1 data[i];
|
calculate_crc(data[i]);
|
calculate_crc(data[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=`DBG_TOP_CRC_LEN -1; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| Line 841... |
Line 885... |
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tdi_pad_i<=#1 1'hz; // tri-state
|
tdi_pad_i<=#1 1'hz; // tri-state
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
|
|
for(i=`DBG_TOP_STATUS_LEN -1; i>=0; i=i-1)
|
|
begin
|
|
gen_clk(1); // Generating 1 clock to read out a status bit.
|
|
status[i] = tdo;
|
|
end
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
for(i=0; i<`DBG_TOP_CRC_LEN -1; i=i+1)
|
gen_clk(1);
|
gen_clk(1);
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1'b1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
if (~crc_match_in)
|
tms_pad_i<=#1 1'b1;
|
|
gen_clk(1); // to update_dr
|
|
tms_pad_i<=#1 1'b0;
|
|
gen_clk(1); // to run_test_idle
|
|
|
|
if (|status)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$write("(*E) (%0t) Chain select error: ", $time);
|
|
casex (status)
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
|
4'bxx1x : $display("Non-existing module selected !!!\n\n", $time);
|
|
4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
|
|
endcase
|
$stop;
|
$stop;
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to update_dr
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to run_test_idle
|
|
end
|
end
|
endtask // chain_select
|
endtask // module_select
|
|
|
|
|
|
|
|
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef WISHBONE_SUPPORTED
|
task debug_wishbone;
|
task debug_wishbone;
|
input [2:0] command;
|
input [`DBG_WB_CMD_LEN -1:0] command;
|
input ready;
|
input ready;
|
input [31:0] addr;
|
input [`DBG_WB_ADR_LEN -1:0] addr;
|
input [15:0] length;
|
input [`DBG_WB_LEN_LEN -1:0] length;
|
input gen_crc_err;
|
input gen_crc_err;
|
input [99:0] text;
|
input [99:0] text;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
$write("(%0t) Task debug_wishbone: ", $time);
|
$write("(%0t) Task debug_wishbone: ", $time);
|
|
|
test_text = text;
|
test_text = text;
|
|
|
case (command)
|
case (command)
|
`WB_STATUS :
|
|
begin
|
|
$display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text);
|
|
debug_wishbone_status(command, gen_crc_err);
|
|
last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS";
|
|
end
|
|
`WB_READ8 :
|
`WB_READ8 :
|
begin
|
begin
|
$display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
$display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8";
|
last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8";
|
| Line 943... |
Line 991... |
|
|
|
|
|
|
|
|
task debug_wishbone_set_addr;
|
task debug_wishbone_set_addr;
|
input [2:0] command;
|
input [`DBG_WB_CMD_LEN -1:0] command;
|
input [31:0] addr;
|
input [`DBG_WB_ADR_LEN -1:0] addr;
|
input [15:0] length;
|
input [`DBG_WB_LEN_LEN -1:0] length;
|
input gen_crc_err;
|
input gen_crc_err;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
$display("(%0t) Task debug_wishbone_set_addr: ", $time);
|
$display("(%0t) Task debug_wishbone_set_addr: ", $time);
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1'b1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 1'b0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
calculate_crc(1'b0);
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
calculate_crc(command[i]);
|
calculate_crc(command[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=31; i>=0; i=i-1) // address
|
for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1) // address
|
begin
|
begin
|
tdi_pad_i<=#1 addr[i];
|
tdi_pad_i<=#1 addr[i];
|
calculate_crc(addr[i]);
|
calculate_crc(addr[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=15; i>=0; i=i-1) // length
|
for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1) // length
|
begin
|
begin
|
tdi_pad_i<=#1 length[i];
|
tdi_pad_i<=#1 length[i];
|
calculate_crc(length[i]);
|
calculate_crc(length[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| Line 996... |
Line 1044... |
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`DBG_WB_STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1'b1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1'b1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 1'b0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
endtask // debug_wishbone_set_addr
|
endtask // debug_wishbone_set_addr
|
|
|
|
|
| Line 1039... |
Line 1087... |
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
calculate_crc(1'b0);
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
| Line 1064... |
Line 1112... |
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`DBG_WB_STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
| Line 1110... |
Line 1158... |
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
calculate_crc(1'b0);
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
| Line 1194... |
Line 1242... |
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`DBG_WB_STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
| Line 1312... |
Line 1360... |
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
calculate_crc(1'b0);
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
| Line 1343... |
Line 1391... |
end
|
end
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`DBG_CPU_STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
| Line 1385... |
Line 1433... |
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
calculate_crc(1'b0);
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
| Line 1449... |
Line 1497... |
for (i=0; i<len; i=i+1)
|
for (i=0; i<len; i=i+1)
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`DBG_CPU_STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
| Line 1574... |
Line 1622... |
* *
|
* *
|
* Printing the information to the screen *
|
* Printing the information to the screen *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
`ifdef MORE_DBG_INFO
|
always @ (posedge tck_pad_i)
|
always @ (posedge tck_pad_i)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.update_ir)
|
if(dbg_tb.i_tap_top.update_ir)
|
case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
|
case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
|
`EXTEST : $display("\tInstruction EXTEST entered");
|
`EXTEST : $display("\tInstruction EXTEST entered");
|
| Line 1587... |
Line 1636... |
`DEBUG : $display("\tInstruction DEBUG entered");
|
`DEBUG : $display("\tInstruction DEBUG entered");
|
`BYPASS : $display("\tInstruction BYPASS entered");
|
`BYPASS : $display("\tInstruction BYPASS entered");
|
default : $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
default : $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
endcase
|
endcase
|
end
|
end
|
|
`endif
|
|
|
|
|
// We never use following states: exit2_ir, exit2_dr, pause_ir or pause_dr
|
// We never use following states: exit2_ir, exit2_dr, pause_ir or pause_dr
|
always @ (posedge tck_pad_i)
|
always @ (posedge tck_pad_i)
|
begin
|
begin
|
| Line 1605... |
Line 1654... |
|
|
|
|
|
|
|
|
// Detecting CRC error
|
// Detecting CRC error
|
always @ (
|
/*
|
posedge dbg_tb.i_dbg_top.chain_latch_en
|
always @ (
|
`ifdef WISHBONE_SUPPORTED
|
posedge dbg_tb.i_dbg_top.module_latch_en
|
or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
|
`ifdef WISHBONE_SUPPORTED
|
`endif
|
or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
|
`ifdef CPU_SUPPORTED
|
`endif
|
or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
|
`ifdef CPU_SUPPORTED
|
`endif
|
or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
|
)
|
`endif
|
|
)
|
|
|
begin
|
|
#2;
|
begin
|
if (~dbg_tb.i_dbg_top.crc_match)
|
#2;
|
begin
|
if (~dbg_tb.i_dbg_top.crc_match)
|
$display("\t\tCRC ERROR !!!");
|
begin
|
$stop;
|
$display("\t\tCRC ERROR !!!");
|
end
|
$stop;
|
end
|
end
|
|
end
|
|
*/
|
|
|
|
|
endmodule // dbg_tb
|
endmodule // dbg_tb
|
|
|
|
|
