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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 138 and 139

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Line 1... Line 1... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
////  dbg_tb.v                                                    ////
 
////  dbg_tb.v                                                    ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////                                                              ////
 
////  This file is part of the SoC/OpenRISC Development Interface ////
 
////  This file is part of the SoC Debug Interface.               ////
 
////  http://www.opencores.org/projects/DebugInterface/           ////
 
////  http://www.opencores.org/projects/DebugInterface/           ////
 
////                                                              ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////  Author(s):                                                  ////
 
////       Igor Mohor (igorm@opencores.org)                       ////
 
////       Igor Mohor (igorm@opencores.org)                       ////
 
////                                                              ////
 
////                                                              ////
Line 41... Line 41... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.40  2004/03/22 16:36:06  igorm
 
 
 
// Temp version before changing dbg interface.
 
 
 
//
 
// Revision 1.39  2004/03/15 16:17:07  igorm
 
// Revision 1.39  2004/03/15 16:17:07  igorm
 
// 'hz changed to 1'hz because Icarus complains.
 
// 'hz changed to 1'hz because Icarus complains.
 
//
 
//
 
// Revision 1.38  2004/01/30 10:24:02  mohor
 
// Revision 1.38  2004/01/30 10:24:02  mohor
 
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
 
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
Line 179... Line 182... 
`include "tap_defines.v"
 
`include "tap_defines.v"
 
`include "dbg_defines.v"
 
`include "dbg_defines.v"
 
`include "dbg_wb_defines.v"
 
`include "dbg_wb_defines.v"
 
`include "dbg_cpu_defines.v"
 
`include "dbg_cpu_defines.v"
 
 
 
 
 
 
 
`define DBG_TEXT(TEXT)   $display("%0s", TEXT);
 
 
 
//  `DBG_TEXT("Bla bla bla") 
 
 
//  $sformat(dbg_text, "\n\nbla 0x%0x 0x%0x\n\n", 32'h12345678, 16'h543);
 
 
 
//  `DBG_TEXT(dbg_text) 
 
 
 
 
 
 
 
 
 
 
 
 
// Test bench
 
// Test bench
 
module dbg_tb;
 
module dbg_tb;
 
 
 
 
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
 
 
 
 
 
 
reg   [999:0] dbg_text;
 
reg   tms_pad_i;
 
reg   tms_pad_i;
 
reg   tck_pad_i;
 
reg   tck_pad_i;
 
reg   trst_pad_i;
 
reg   trst_pad_i;
 
reg   tdi_pad_i;
 
reg   tdi_pad_i;
 
wire  tdo_pad_o;
 
wire  tdo_pad_o;
Line 203... Line 214... 
wire  mbist_select_o;
 
wire  mbist_select_o;
 
wire  debug_select_o;
 
wire  debug_select_o;
 
 
 
 
 
reg   rst_i;
 
reg   rst_i;
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
`ifdef DBG_WISHBONE_SUPPORTED
 
// WISHBONE common signals
 
// WISHBONE common signals
 
reg   wb_clk_i;
 
reg   wb_clk_i;
 
 
 
 
 
// WISHBONE master interface
 
// WISHBONE master interface
 
wire [31:0] wb_adr_o;
 
wire [31:0] wb_adr_o;
Line 222... Line 233... 
wire        wb_err_i;
 
wire        wb_err_i;
 
wire  [2:0] wb_cti_o;
 
wire  [2:0] wb_cti_o;
 
wire  [1:0] wb_bte_o;
 
wire  [1:0] wb_bte_o;
 
`endif
 
`endif
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
`ifdef DBG_CPU_SUPPORTED
 
// CPU signals
 
// CPU signals
 
wire        cpu_clk_i;
 
wire        cpu_clk_i;
 
wire [31:0] cpu_addr_o;
 
wire [31:0] cpu_addr_o;
 
wire [31:0] cpu_data_i;
 
wire [31:0] cpu_data_i;
 
wire [31:0] cpu_data_o;
 
wire [31:0] cpu_data_o;
 
wire        cpu_bp_i;
 
wire        cpu_bp_i;
 
wire        cpu_stall_o;
 
wire        cpu_stall_o;
 
wire        cpu_stall_all_o;
 
 
 
wire        cpu_stb_o;
 
wire        cpu_stb_o;
 
wire  [`CPU_NUM -1:0]  cpu_sel_o;
 
 
 
wire        cpu_we_o;
 
wire        cpu_we_o;
 
wire        cpu_ack_i;
 
wire        cpu_ack_i;
 
wire        cpu_rst_o;
 
wire        cpu_rst_o;
 
`endif
 
`endif
 
 
 
 
 
// Text used for easier debugging
 
// Text used for easier debugging
 
reg [199:0] test_text;
 
reg [199:0] test_text;
 
reg   [2:0] last_wb_cmd;
 
reg [`DBG_WB_CMD_LEN -1:0]  last_wb_cmd;
 
 
 
reg [`DBG_CPU_CMD_LEN -1:0] last_cpu_cmd;
 
reg [199:0] last_wb_cmd_text;
 
reg [199:0] last_wb_cmd_text;
 
 
 
reg [199:0] last_cpu_cmd_text;
 
 
 
 
 
reg  [31:0] wb_data [0:4095];   // Data that is written to (read from) wishbone is stored here. 
reg  [31:0] wb_data [0:4095];   // Data that is written to (read from) wishbone is stored here. 
 
 
 
 
 
 
 
 
 
 
 
Line 263... Line 274... 
 
 
 
 
wire crc_match_in;
 
wire crc_match_in;
 
reg [31:0] crc_in;
 
reg [31:0] crc_in;
 
reg [31:0] crc_out;
 
reg [31:0] crc_out;
 
reg [`DBG_TOP_STATUS_LEN -1:0] status;
 
reg [`DBG_TOP_STATUS_LEN -1:0] status;
 
 
 
reg [`DBG_WB_STATUS_LEN -1:0]  status_wb;
 
 
 
reg [`DBG_CPU_STATUS_LEN -1:0] status_cpu;
 
 
 
 
 
 
 
reg [`DBG_WB_ACC_TYPE_LEN -1:0]  read_acc_type;
 
 
 
reg [`DBG_WB_ADR_LEN -1:0]       read_addr;
 
 
 
reg [`DBG_WB_LEN_LEN -1:0]       read_length;
 
 
 
reg [`DBG_CPU_CTRL_LEN -1:0]     read_ctrl_reg;
 
 
 
 
 
wire tdo;
 
wire tdo;
 
 
 
 
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
 
 
 
 
Line 315... Line 333... 
                    .update_dr_i      (update_dr_o),
 
                    .update_dr_i      (update_dr_o),
 
 
 
 
 
                    // Instructions
 
                    // Instructions
 
                    .debug_select_i   (debug_select_o)
 
                    .debug_select_i   (debug_select_o)
 
 
 
 
 
                    `ifdef WISHBONE_SUPPORTED
 
                    `ifdef DBG_WISHBONE_SUPPORTED
 
                    // WISHBONE common signals
 
                    // WISHBONE common signals
 
                    ,
 
                    ,
 
                    .wb_clk_i         (wb_clk_i),
 
                    .wb_clk_i         (wb_clk_i),
 
 
 
 
 
                    // WISHBONE master interface
 
                    // WISHBONE master interface
Line 335... Line 353... 
                    .wb_err_i         (wb_err_i),
 
                    .wb_err_i         (wb_err_i),
 
                    .wb_cti_o         (wb_cti_o),
 
                    .wb_cti_o         (wb_cti_o),
 
                    .wb_bte_o         (wb_bte_o)
 
                    .wb_bte_o         (wb_bte_o)
 
                    `endif
 
                    `endif
 
 
 
 
 
                    `ifdef CPU_SUPPORTED
 
                    `ifdef DBG_CPU_SUPPORTED
 
                    // CPU signals
 
                    // CPU signals
 
                    ,
 
                    ,
 
                    .cpu_clk_i        (cpu_clk_i),
 
                    .cpu_clk_i        (cpu_clk_i),
 
                    .cpu_addr_o       (cpu_addr_o),
 
                    .cpu_addr_o       (cpu_addr_o),
 
                    .cpu_data_i       (cpu_data_i),
 
                    .cpu_data_i       (cpu_data_i),
 
                    .cpu_data_o       (cpu_data_o),
 
                    .cpu_data_o       (cpu_data_o),
 
                    .cpu_bp_i         (cpu_bp_i),
 
                    .cpu_bp_i         (cpu_bp_i),
 
                    .cpu_stall_o      (cpu_stall_o),
 
                    .cpu_stall_o      (cpu_stall_o),
 
                    .cpu_stall_all_o  (cpu_stall_all_o),
 
 
 
                    .cpu_stb_o        (cpu_stb_o),
 
                    .cpu_stb_o        (cpu_stb_o),
 
                    .cpu_sel_o        (cpu_sel_o),
 
 
 
                    .cpu_we_o         (cpu_we_o),
 
                    .cpu_we_o         (cpu_we_o),
 
                    .cpu_ack_i        (cpu_ack_i),
 
                    .cpu_ack_i        (cpu_ack_i),
 
                    .cpu_rst_o        (cpu_rst_o)
 
                    .cpu_rst_o        (cpu_rst_o)
 
                    `endif
 
                    `endif
 
 
 
 
 
 
 
 
 
 
 
 
 
                   );
 
                   );
 
 
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
`ifdef DBG_WISHBONE_SUPPORTED
 
wb_slave_behavioral wb_slave
 
wb_slave_behavioral wb_slave
 
                   (
 
                   (
 
                    .CLK_I            (wb_clk_i),
 
                    .CLK_I            (wb_clk_i),
 
                    .RST_I            (rst_i),
 
                    .RST_I            (rst_i),
 
                    .ACK_O            (wb_ack_i),
 
                    .ACK_O            (wb_ack_i),
Line 377... Line 393... 
                    .CAB_I            (1'b0)
 
                    .CAB_I            (1'b0)
 
                   );
 
                   );
 
`endif
 
`endif
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
`ifdef DBG_CPU_SUPPORTED
 
cpu_behavioral i_cpu_behavioral
 
cpu_behavioral i_cpu_behavioral
 
                   (
 
                   (
 
                    // CPU signals
 
                    // CPU signals
 
                    .cpu_rst_i        (rst_i),
 
                    .cpu_rst_i        (rst_i),
 
                    .cpu_clk_o        (cpu_clk_i),
 
                    .cpu_clk_o        (cpu_clk_i),
 
                    .cpu_addr_i       (cpu_addr_o),
 
                    .cpu_addr_i       (cpu_addr_o),
 
                    .cpu_data_o       (cpu_data_i),
 
                    .cpu_data_o       (cpu_data_i),
 
                    .cpu_data_i       (cpu_data_o),
 
                    .cpu_data_i       (cpu_data_o),
 
                    .cpu_bp_o         (cpu_bp_i),
 
                    .cpu_bp_o         (cpu_bp_i),
 
                    .cpu_stall_i      (cpu_stall_o),
 
                    .cpu_stall_i      (cpu_stall_o),
 
                    .cpu_stall_all_i  (cpu_stall_all_o),
 
 
 
                    .cpu_stb_i        (cpu_stb_o),
 
                    .cpu_stb_i        (cpu_stb_o),
 
                    .cpu_sel_i        (cpu_sel_o),
 
 
 
                    .cpu_we_i         (cpu_we_o),
 
                    .cpu_we_i         (cpu_we_o),
 
                    .cpu_ack_o        (cpu_ack_i),
 
                    .cpu_ack_o        (cpu_ack_i),
 
                    .cpu_rst_o        (cpu_rst_o)
 
                    .cpu_rst_o        (cpu_rst_o)
 
                   );
 
                   );
 
`endif
 
`endif
Line 423... Line 437... 
  rst_i = 1'b1;
 
  rst_i = 1'b1;
 
  #1000;
 
  #1000;
 
  rst_i = 1'b0;
 
  rst_i = 1'b0;
 
 
 
 
 
  // Initial values for wishbone slave model
 
  // Initial values for wishbone slave model
 
  `ifdef WISHBONE_SUPPORTED
 
  `ifdef DBG_WISHBONE_SUPPORTED
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
//  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h35, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  `endif
 
  `endif
 
  #1 test_enabled<=#1 1'b1;
 
  #1 test_enabled<=#1 1'b1;
 
end
 
end
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
`ifdef DBG_WISHBONE_SUPPORTED
 
initial
 
initial
 
begin
 
begin
 
  wb_clk_i = 1'b0;
 
  wb_clk_i = 1'b0;
 
  forever #5 wb_clk_i = ~wb_clk_i;
 
  forever #5 wb_clk_i = ~wb_clk_i;
 
end
 
end
Line 455... Line 470... 
  reset_tap;
 
  reset_tap;
 
 
 
 
 
  #500;
 
  #500;
 
  goto_run_test_idle;
 
  goto_run_test_idle;
 
 
 
 
 
  `ifdef CPU_SUPPORTED
 
//  `ifdef DBG_CPU_SUPPORTED
 
  // Test stall signal
 
//  // Test stall signal
 
  stall_test;
 
//  stall_test;
 
  `endif
 
//  `endif
 
 
 
 
 
  // Testing read and write to internal registers
 
  // Testing read and write to internal registers
 
  #10000;
 
  #10000;
 
 
 
 
 
  id_test;
 
  id_test;
Line 476... Line 491... 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  #100000;
 
  #100000;
 
  `ifdef WISHBONE_SUPPORTED
 
  `ifdef DBG_WISHBONE_SUPPORTED
 
  module_select(`WISHBONE_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
  module_select(`DBG_TOP_WISHBONE_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h3, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
  debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  test_text = "debug_wishbone_rd_comm";
 
 
 
  debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
 
 
 
  $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
 
 
 
  debug_wishbone_go(1'b0, 1'b0);
 
 
 
  debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
 
 
 
  $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
 
 
 
 
 
 
 
  debug_wishbone_go(1'b0, 1'b0);
 
 
 
 
 
 
 
  #100000;
 
 
 
//  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345224, 16'h7, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345223, 16'h8, 1'b0, "read8 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  #100000;
 
  #100000;
 
 
 
  debug_wishbone_go(1'b0, 1'b0);
 
 
 
 
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
 
 
  #10000;
 
/*
 
 
 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
  debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
//
 
 
 
//  debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  #10000;
 
 
 
 
 
  #10000;
 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
  wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2);   // (`ERR_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`DBG_WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}  
//  debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
  `endif  // WISHBONE_SUPPORTED
 
//  debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  `ifdef CPU_SUPPORTED
 
  #10000;
 
 
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
*/
 
 
 
  `endif  // DBG_WISHBONE_SUPPORTED
 
 
 
 
 
 
 
  `ifdef DBG_CPU_SUPPORTED
 
  #10000;
 
  #10000;
 
  module_select(`CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
  module_select(`DBG_TOP_CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  // Select cpu0
 
  // Select cpu0
 
  #10000;
 
 
 
  debug_cpu(`CPU_WRITE_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "select cpu 0"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  // Read register
 
  // Read register
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_READ_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "cpu_read_reg"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // Stall cpu0
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "stall cpu0"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
  // Read register
 
 
 
  #10000;
 
 
 
 
 
 
 
  // Reset cpu on
 
 
 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text} igor !!! poglej endian
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write to cpu 32-bit
 
  // Reset cpu off
 
 
 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
 
 
  // Stall cpu
 
 
 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // read from cpu 32-bit
 
  debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
 
 
  // Stall cpu0
 
 
 
  debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
 
 
 
  $display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write to cpu 8-bit
 
  debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
  // write to cpu 32-bit
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
  debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // read from cpu 8-bit
 
  // read from cpu 32-bit
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
  `endif
 
 
 
 
 
 
 
 
 
  `endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Line 621... Line 654... 
  #1000 $stop;
 
  #1000 $stop;
 
 
 
 
 
end
 
end
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
`ifdef DBG_CPU_SUPPORTED
 
task stall_test;
 
task stall_test;
 
  integer i;
 
  integer i;
 
 
 
 
 
  begin
 
  begin
 
    test_text = "stall_test";
 
    test_text = "stall_test";
Line 643... Line 676... 
    gen_clk(1);
 
    gen_clk(1);
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
 
 
 
 
    // Unstall with register
 
    // Unstall with register
 
    set_instruction(`DEBUG);
 
    set_instruction(`DEBUG);
 
    module_select(`CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
    module_select(`DBG_TOP_CPU_DEBUG_MODULE, 1'b0);   // {module_id, gen_crc_err}
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
    debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(0); // reset?
 
    #1 check_stall(0); // reset?
 
 
 
 
 
    // Set stall with register
 
    // Set stall with register
 
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(0); // reset?
 
    #1 check_stall(0); // reset?
 
    debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
 
 
 
 
    // Unstall with register
 
    // Unstall with register
 
    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
 
// igor !!!    debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
    debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
    #1 check_stall(0); // reset?
 
    #1 check_stall(0); // reset?
 
 
 
 
 
    $display("\n\n(%0t) stall_test passed\n\n", $time);
 
    $display("\n\n(%0t) stall_test passed\n\n", $time);
 
  end
 
  end
 
endtask   // stall_test
 
endtask   // stall_test
Line 694... Line 727... 
  reg [31:0] addr;
 
  reg [31:0] addr;
 
  begin
 
  begin
 
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
 
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
 
      begin
 
      begin
 
        addr = start_addr + i;
 
        addr = start_addr + i;
 
        `ifdef WISHBONE_SUPPORTED
 
        `ifdef DBG_WISHBONE_SUPPORTED
 
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
 
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
 
        `endif
 
        `endif
 
      end
 
      end
 
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
 
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
 
      begin
 
      begin
Line 714... Line 747... 
    $display("\n\n(%0t) TEST: id_test", $time);
 
    $display("\n\n(%0t) TEST: id_test", $time);
 
 
 
 
 
    set_instruction(`IDCODE);
 
    set_instruction(`IDCODE);
 
    read_id_code(id);
 
    read_id_code(id);
 
 
 
 
 
    `ifdef MORE_DBG_INFO
 
    `ifdef DBG_MORE_INFO
 
      $display("\tRead ID     = 0x%0x", id);
 
      $display("\tRead ID     = 0x%0x", id);
 
      $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
 
      $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
 
    `endif
 
    `endif
 
 
 
 
 
    if (id==`IDCODE_VALUE)
 
    if (id==`IDCODE_VALUE)
Line 769... Line 802... 
  input [3:0] instr;
 
  input [3:0] instr;
 
  integer i;
 
  integer i;
 
 
 
 
 
  begin
 
  begin
 
    case (instr)
 
    case (instr)
 
      `ifdef MORE_DBG_INFO
 
      `ifdef DBG_MORE_INFO
 
        `EXTEST          : $display("(%0t) Task set_instruction (EXTEST)", $time);
 
        `EXTEST          : $display("(%0t) Task set_instruction (EXTEST)", $time);
 
        `SAMPLE_PRELOAD  : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
 
        `SAMPLE_PRELOAD  : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
 
        `IDCODE          : $display("(%0t) Task set_instruction (IDCODE)", $time);
 
        `IDCODE          : $display("(%0t) Task set_instruction (IDCODE)", $time);
 
        `DEBUG           : $display("(%0t) Task set_instruction (DEBUG)", $time);
 
        `DEBUG           : $display("(%0t) Task set_instruction (DEBUG)", $time);
 
        `MBIST           : $display("(%0t) Task set_instruction (MBIST)", $time);
 
        `MBIST           : $display("(%0t) Task set_instruction (MBIST)", $time);
Line 818... Line 851... 
// Reads the ID code
 
// Reads the ID code
 
task read_id_code;
 
task read_id_code;
 
  output [31:0] code;
 
  output [31:0] code;
 
  reg    [31:0] code;
 
  reg    [31:0] code;
 
  begin
 
  begin
 
    `ifdef MORE_DBG_INFO
 
    `ifdef DBG_MORE_INFO
 
      $display("(%0t) Task read_id_code", $time);
 
      $display("(%0t) Task read_id_code", $time);
 
    `endif
 
    `endif
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 0;
Line 844... Line 877... 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
// sets the selected module and goes to the RunTestIdle state
 
// sets the selected module and goes to the RunTestIdle state
 
task module_select;
 
task module_select;
 
  input [`MODULE_ID_LENGTH -1:0]  data;
 
  input [`DBG_TOP_MODULE_ID_LENGTH -1:0]  data;
 
  input                           gen_crc_err;
 
  input                           gen_crc_err;
 
  integer                         i;
 
  integer                         i;
 
 
 
 
 
  begin
 
  begin
 
    case (data)
 
    case (data)
 
      `CPU_DEBUG_MODULE      : $display("(%0t) Task module_select (CPU_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
 
      `DBG_TOP_CPU_DEBUG_MODULE      : $display("(%0t) Task module_select (DBG_TOP_CPU_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
 
      `WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
 
      `DBG_TOP_WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (DBG_TOP_WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
 
      default                : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
 
      default                : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
 
    endcase
 
    endcase
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
Line 866... Line 899... 
    crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
    crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
    tdi_pad_i<=#1 1'b1; // module_select bit
 
    tdi_pad_i<=#1 1'b1; // module_select bit
 
    calculate_crc(1'b1);
 
    calculate_crc(1'b1);
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
    for(i=`MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
 
    for(i=`DBG_TOP_MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
 
    begin
 
    begin
 
      tdi_pad_i<=#1 data[i];
 
      tdi_pad_i<=#1 data[i];
 
      calculate_crc(data[i]);
 
      calculate_crc(data[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
Line 909... Line 942... 
    if (|status)
 
    if (|status)
 
      begin
 
      begin
 
        $write("(*E) (%0t) Chain select error: ", $time);
 
        $write("(*E) (%0t) Chain select error: ", $time);
 
        casex (status)
 
        casex (status)
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
          4'bx1xx : $display("Non-existing module selected !!!\n\n", $time);
 
          4'bxx1x : $display("Non-existing module selected !!!\n\n", $time);
 
          4'bxx1x : $display("Status[1] should be 1'b0 !!!\n\n", $time);
 
          4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
 
          4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
 
        endcase
 
        endcase
 
        $stop;
 
        $stop;
 
      end
 
      end
 
  end
 
  end
 
endtask   // module_select
 
endtask   // module_select
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
`ifdef DBG_WISHBONE_SUPPORTED
 
task debug_wishbone;
 
task debug_wishbone;
 
  input [`DBG_WB_CMD_LEN -1:0]   command;
 
  input [`DBG_WB_CMD_LEN -1:0]   command;
 
  input         ready;
 
  input         ready;
 
  input [`DBG_WB_ADR_LEN -1:0]  addr;
 
  input [`DBG_WB_ADR_LEN -1:0]  addr;
 
  input [`DBG_WB_LEN_LEN -1:0]  length;
 
  input [`DBG_WB_LEN_LEN -1:0]  length;
Line 937... Line 970... 
   $write("(%0t) Task debug_wishbone: ", $time);
 
   $write("(%0t) Task debug_wishbone: ", $time);
 
 
 
 
 
    test_text = text;
 
    test_text = text;
 
 
 
 
 
    case (command)
 
    case (command)
 
      `WB_READ8    :
 
      `DBG_WB_READ8    :
 
        begin
 
        begin
 
          $display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_READ8, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_READ8;  last_wb_cmd_text = "WB_READ8";
 
          last_wb_cmd = `DBG_WB_READ8;  last_wb_cmd_text = "DBG_WB_READ8";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_READ16   :
 
      `DBG_WB_READ16   :
 
        begin
 
        begin
 
          $display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_READ16, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_READ16;  last_wb_cmd_text = "WB_READ16";
 
          last_wb_cmd = `DBG_WB_READ16;  last_wb_cmd_text = "DBG_WB_READ16";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_READ32   :
 
      `DBG_WB_READ32   :
 
        begin
 
        begin
 
          $display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_READ32, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_READ32;  last_wb_cmd_text = "WB_READ32";
 
          last_wb_cmd = `DBG_WB_READ32;  last_wb_cmd_text = "DBG_WB_READ32";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_WRITE8   :
 
      `DBG_WB_WRITE8   :
 
        begin
 
        begin
 
          $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_WRITE8, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_WRITE8;  last_wb_cmd_text = "WB_WRITE8";
 
          last_wb_cmd = `DBG_WB_WRITE8;  last_wb_cmd_text = "DBG_WB_WRITE8";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_WRITE16  :
 
      `DBG_WB_WRITE16  :
 
        begin
 
        begin
 
          $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_WRITE16, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_WRITE16;  last_wb_cmd_text = "WB_WRITE16";
 
          last_wb_cmd = `DBG_WB_WRITE16;  last_wb_cmd_text = "DBG_WB_WRITE16";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_WRITE32  :
 
      `DBG_WB_WRITE32  :
 
        begin
 
        begin
 
          $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_wishbone_set_addr(command, addr, length, gen_crc_err);
 
          debug_wishbone_wr_comm(`DBG_WB_WRITE32, addr, length, gen_crc_err);
 
          last_wb_cmd = `WB_WRITE32;  last_wb_cmd_text = "WB_WRITE32";
 
          last_wb_cmd = `DBG_WB_WRITE32;  last_wb_cmd_text = "DBG_WB_WRITE32";
 
 
 
#10000;
 
 
 
          debug_wishbone_go(ready, gen_crc_err);
 
        end
 
        end
 
      `WB_GO       :
 
      default:
 
        begin
 
        begin
 
          $display("wb_go, ready=%0d, gen_crc_err=%0d (%0s))", ready, gen_crc_err, text);
 
          $display("(*E) debug_wishbone : Unsupported instruction !!!");
 
          debug_wishbone_go(command, ready, gen_crc_err);
 
          $stop;
 
//          $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text);
 
 
 
//          debug_wishbone_go_tmp(command, crc);
 
 
 
          last_wb_cmd = `WB_GO;  last_wb_cmd_text = "WB_GO";
 
 
 
        end
 
        end
 
    endcase
 
    endcase
 
  end
 
  end
 
endtask       // debug_wishbone
 
endtask       // debug_wishbone
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_wishbone_set_addr;
 
task debug_wishbone_wr_comm;
 
  input [`DBG_WB_CMD_LEN -1:0]  command;
 
  input [`DBG_WB_ACC_TYPE_LEN -1:0]   acc_type;
 
  input [`DBG_WB_ADR_LEN -1:0]  addr;
 
  input [`DBG_WB_ADR_LEN -1:0]  addr;
 
  input [`DBG_WB_LEN_LEN -1:0]  length;
 
  input [`DBG_WB_LEN_LEN -1:0]  length;
 
  input                         gen_crc_err;
 
  input                         gen_crc_err;
 
  integer i;
 
  integer i;
 
 
 
  reg   [`DBG_WB_CMD_LEN -1:0]        command;
 
 
 
 
 
  begin
 
  begin
 
    $display("(%0t) Task debug_wishbone_set_addr: ", $time);
 
    $display("(%0t) Task debug_wishbone_wr_comm: ", $time);
 
 
 
 
 
 
 
    command = `DBG_WB_WR_COMM;
 
    tms_pad_i<=#1 1'b1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 1'b0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(2);  // we are in shiftDR
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
Line 1018... Line 1062... 
      tdi_pad_i<=#1 command[i]; // command
 
      tdi_pad_i<=#1 command[i]; // command
 
      calculate_crc(command[i]);
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 acc_type[i]; // command
 
 
 
      calculate_crc(acc_type[i]);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
 
    begin
 
    begin
 
      tdi_pad_i<=#1 addr[i];
 
      tdi_pad_i<=#1 addr[i];
 
      calculate_crc(addr[i]);
 
      calculate_crc(addr[i]);
 
      gen_clk(1);
 
      gen_clk(1);
Line 1045... Line 1096... 
    end
 
    end
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
    gen_clk(`DBG_WB_STATUS_LEN);       // Generating 4 clocks to read out status.
 
 
 
 
 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
 
 
 
      begin
 
 
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_wb[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_wb)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_wishbone_wr_comm error: ", $time);
 
 
 
        casex (status_wb)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
 
 
 
        endcase
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
 
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    begin
 
    begin
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to exit1_dr
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
    if (~crc_match_in)
 
 
 
      begin
 
 
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to update_dr
 
    gen_clk(1);         // to update_dr
 
    tms_pad_i<=#1 1'b0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_wishbone_set_addr
 
endtask       // debug_wishbone_wr_comm
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_wishbone_status;
 
task debug_wishbone_rd_comm;
 
  input [2:0]   command;
 
  output [`DBG_WB_ACC_TYPE_LEN -1:0]  acc_type;
 
  input         gen_crc_err;
 
  output [`DBG_WB_ADR_LEN -1:0]       addr;
 
 
 
  output [`DBG_WB_LEN_LEN -1:0]       length;
 
  integer i;
 
  integer i;
 
 
 
  reg   [`DBG_WB_CMD_LEN -1:0]        command;
 
 
 
 
 
  begin
 
  begin
 
    $display("(%0t) Task debug_wishbone_status: ", $time);
 
    $display("(%0t) Task debug_wishbone_rd_comm: ", $time);
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    command = `DBG_WB_RD_COMM;
 
 
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(2);  // we are in shiftDR
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    calculate_crc(1'b0);
 
    calculate_crc(1'b0);
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
    for(i=2; i>=0; i=i-1)
 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      tdi_pad_i<=#1 command[i]; // command
 
      tdi_pad_i<=#1 command[i]; // command
 
      calculate_crc(command[i]);
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=31; i>=0; i=i-1)
 
    for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
 
      tdi_pad_i<=#1 crc_out[i];
 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
 
 
 
      else
 
 
 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
 
 
 
 
 
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
 
 
 
 
    gen_clk(`DBG_WB_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      gen_clk(1);
 
 
 
      acc_type[i] = tdo;
 
 
 
    end
 
 
 
 
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1)       // address
 
    begin
 
    begin
 
      gen_clk(1);
 
      gen_clk(1);
 
 
 
      addr[i] = tdo;
 
    end
 
    end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1)       // length
 
    gen_clk(1);         // to exit1_dr
 
    begin
 
 
 
      gen_clk(1);
 
 
 
      length[i] = tdo;
 
 
 
    end
 
 
 
 
 
    if (~crc_match_in)
 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
 
      begin
 
      begin
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_wb[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_wb)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_wishbone_rd_comm: ", $time);
 
 
 
        casex (status_wb)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Unknown command !!!\n\n", $time);
 
 
 
        endcase
 
        $stop;
 
        $stop;
 
      end
 
      end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
 
 
 
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
 
 
    begin
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to update_dr
 
    gen_clk(1);         // to update_dr
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_wishbone_status
 
endtask       // debug_wishbone_rd_comm
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_wishbone_go;
 
task debug_wishbone_go;
 
  input [2:0]   command;
 
 
 
  input         wait_for_wb_ready;
 
  input         wait_for_wb_ready;
 
  input         gen_crc_err;
 
  input         gen_crc_err;
 
  integer i;
 
  integer i;
 
  reg   [4:0]   bit_pointer;
 
  reg   [4:0]   bit_pointer;
 
  integer       word_pointer;
 
  integer       word_pointer;
 
  reg  [31:0]   tmp_data;
 
  reg  [31:0]   tmp_data;
 
 
 
  reg [`DBG_WB_CMD_LEN -1:0]        command;
 
 
 
 
 
 
 
 
 
  begin
 
  begin
 
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
 
 
    command = `DBG_WB_GO;
 
    word_pointer = 0;
 
    word_pointer = 0;
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(2);  // we are in shiftDR
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    calculate_crc(1'b0);
 
    calculate_crc(1'b0);
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
    for(i=2; i>=0; i=i-1)
 
    for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      tdi_pad_i<=#1 command[i]; // command
 
      tdi_pad_i<=#1 command[i]; // command
 
      calculate_crc(command[i]);
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
 
 
 
 
    if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
 
    if ((last_wb_cmd == `DBG_WB_WRITE8) | (last_wb_cmd == `DBG_WB_WRITE16) | (last_wb_cmd == `DBG_WB_WRITE32))  // When WB_WRITEx was previously activated, data needs to be shifted.
 
      begin
 
      begin
 
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
 
        for (i=0; i<((dbg_tb.i_dbg_top.i_dbg_wb.len_var) << 3); i=i+1)
 
          begin
 
          begin
 
            tmp_data = wb_data[word_pointer];
 
            tmp_data = wb_data[word_pointer];
 
            if ((!(i%32)) && (i>0))
 
            if ((!(i%32)) && (i>0))
 
              begin
 
              begin
 
                word_pointer = word_pointer + 1;
 
                word_pointer = word_pointer + 1;
Line 1187... Line 1281... 
            gen_clk(1);
 
            gen_clk(1);
 
 
 
 
 
          end
 
          end
 
      end
 
      end
 
 
 
 
 
    for(i=31; i>=1; i=i-1)
 
    for(i=`DBG_WB_CRC_LEN -1; i>=1; i=i-1)
 
    begin
 
    begin
 
      tdi_pad_i<=#1 crc_out[i];
 
      tdi_pad_i<=#1 crc_out[i];
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
Line 1200... Line 1294... 
    else
 
    else
 
      tdi_pad_i<=#1 crc_out[0];    // ok crc
 
      tdi_pad_i<=#1 crc_out[0];    // ok crc
 
 
 
 
 
    if (wait_for_wb_ready)
 
    if (wait_for_wb_ready)
 
      begin
 
      begin
 
        tms_pad_i<=#1 1;
 
        tms_pad_i<=#1 1'b1;
 
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
 
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
 
        tms_pad_i<=#1 0;
 
        tms_pad_i<=#1 1'b0;
 
        gen_clk(1);       // to pause_dr
 
        gen_clk(1);       // to pause_dr
 
 
 
 
 
        #2;             // wait a bit for tdo to activate
 
        #2;             // wait a bit for tdo to activate
 
        while (tdo)     // waiting for wb to send "ready"
 
        while (tdo)     // waiting for wb to send "ready"
 
        begin
 
        begin
 
          gen_clk(1);       // staying in pause_dr
 
          gen_clk(1);       // staying in pause_dr
 
        end
 
        end
 
 
 
 
 
        tms_pad_i<=#1 1;
 
        tms_pad_i<=#1 1'b1;
 
        gen_clk(1);       // to exit2_dr
 
        gen_clk(1);       // to exit2_dr
 
        tms_pad_i<=#1 0;
 
        tms_pad_i<=#1 1'b0;
 
        gen_clk(1);       // to shift_dr
 
        gen_clk(1);       // to shift_dr
 
      end
 
      end
 
    else
 
    else
 
      begin
 
      begin
 
        gen_clk(1);       // Last CRC is shifted on this clk
 
        gen_clk(1);       // Last CRC is shifted on this clk
 
      end
 
      end
 
 
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
    tdi_pad_i<=#1 1'hz;
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    crc_in = {`DBG_WB_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
 
 
 
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_READx was previously activated, data needs to be shifted.
 
    if ((last_wb_cmd == `DBG_WB_READ8) | (last_wb_cmd == `DBG_WB_READ16) | (last_wb_cmd == `DBG_WB_READ32))  // When WB_READx was previously activated, data needs to be shifted.
 
      begin
 
      begin
 
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
 
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
 
        word_pointer = 0; // Reset pointer
 
        word_pointer = 0; // Reset pointer
 
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
 
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
 
          begin
 
          begin
Line 1242... Line 1336... 
              end
 
              end
 
          end
 
          end
 
      end
 
      end
 
 
 
 
 
 
 
 
 
    gen_clk(`DBG_WB_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
 
 
 
      begin
 
 
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_wb[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_wb)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_wishbone_go error: ", $time);
 
 
 
        casex (status_wb)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
 
 
 
        endcase
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
 
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    begin
 
    begin
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to exit1_dr
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
    if (~crc_match_in)
 
    if (~crc_match_in)
 
      begin
 
      begin
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
        $stop;
 
        $stop;
 
      end
 
      end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to update_dr
 
    gen_clk(1);         // to update_dr
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_wishbone_go
 
endtask       // debug_wishbone_go
 
 
 
 
 
 
 
 
 
`endif // WISHBONE_SUPPORTED
 
`endif // DBG_WISHBONE_SUPPORTED
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
`ifdef DBG_CPU_SUPPORTED
 
task debug_cpu;
 
task debug_cpu;
 
  input [2:0]   command;
 
  input [`DBG_CPU_CMD_LEN -1:0]   command;
 
  input [31:0]  addr;
 
  input                           ready;
 
  input [31:0]  data;
 
  input [`DBG_CPU_ADR_LEN -1:0]   addr;
 
 
 
  input [`DBG_CPU_LEN_LEN -1:0]   length;
 
  input         gen_crc_err;
 
  input         gen_crc_err;
 
  output [31:0] result;
 
  input [99:0]                    text;
 
  input [199:0]  text;
 
 
 
  integer i;
 
  integer i;
 
 
 
 
 
  begin
 
  begin
 
   $write("(%0t) Task debug_cpu: ", $time);
 
   $write("(%0t) Task debug_cpu: ", $time);
 
 
 
 
 
    test_text = text;
 
    test_text = text;
 
 
 
 
 
    case (command)
 
    case (command)
 
//      `WB_STATUS   : 
      `DBG_CPU_READ   :
 
//        begin
 
 
 
//          $display("wb_status (gen_crc_err=%0d (%0s))", gen_crc_err, text);
 
 
 
//          debug_wishbone_status(command, gen_crc_err);
 
 
 
//          last_wb_cmd = `WB_STATUS;  last_wb_cmd_text = "WB_STATUS";
 
 
 
//        end 
 
 
      `CPU_READ_REG   :
 
 
 
        begin
 
 
 
          $display("cpu_read_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
 
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
 
 
          last_wb_cmd = `CPU_READ_REG;  last_wb_cmd_text = "CPU_READ_REG";
 
 
 
        end
 
 
 
      `CPU_WRITE_REG  :
 
 
 
        begin
 
 
 
          $display("cpu_write_reg (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
 
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
 
 
          last_wb_cmd = `CPU_WRITE_REG;  last_wb_cmd_text = "CPU_WRITE_REG";
 
 
 
        end
 
 
 
      `CPU_READ8      :
 
 
 
        begin
 
 
 
          $display("cpu_read8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
 
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
 
 
          last_wb_cmd = `CPU_READ8;  last_wb_cmd_text = "CPU_READ8";
 
 
 
        end
 
 
 
      `CPU_READ32     :
 
 
 
        begin
 
 
 
          $display("cpu_read32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
 
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
 
 
          last_wb_cmd = `CPU_READ32;  last_wb_cmd_text = "CPU_READ32";
 
 
 
        end
 
 
 
      `CPU_WRITE8     :
 
 
 
        begin
 
 
 
          $display("cpu_write8 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
 
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
 
 
          last_wb_cmd = `CPU_WRITE8;  last_wb_cmd_text = "CPU_WRITE8";
 
 
 
        end
 
 
 
      `CPU_WRITE32    :
 
 
 
        begin
 
        begin
 
          $display("cpu_write32 (adr=0x%0x, gen_crc_err=%0d (%0s))", addr, gen_crc_err, text);
 
          $display("cpu_read (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_cpu_set_addr(command, addr, gen_crc_err);
 
          debug_cpu_wr_comm(`DBG_CPU_READ, addr, length, gen_crc_err);
 
          last_wb_cmd = `CPU_WRITE32;  last_wb_cmd_text = "CPU_WRITE32";
 
          last_cpu_cmd = `DBG_CPU_READ;  last_cpu_cmd_text = "DBG_CPU_READ";
 
 
 
#10000;
 
 
 
          debug_cpu_go(ready, gen_crc_err);
 
        end
 
        end
 
      `CPU_GO         :
 
      `DBG_CPU_WRITE  :
 
        begin
 
        begin
 
          $display("cpu_go, data = 0x%0x, gen_crc_err=%0d (%0s))", data, gen_crc_err, text);
 
          $display("cpu_write (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
 
          debug_cpu_go(command, data, gen_crc_err);
 
          debug_cpu_wr_comm(`DBG_CPU_WRITE, addr, length, gen_crc_err);
 
          last_wb_cmd = `CPU_GO;  last_wb_cmd_text = "CPU_GO";
 
          last_cpu_cmd = `DBG_CPU_WRITE;  last_cpu_cmd_text = "DBG_CPU_WRITE";
 
 
 
#10000;
 
 
 
          debug_cpu_go(ready, gen_crc_err);
 
        end
 
        end
 
      default     :
 
      default     :
 
        begin
 
        begin
 
          $display("\t\tERROR: Non-existing command while debugging %0s", gen_crc_err, text);
 
          $display("(*E) debug_cpu : Unsupported instruction !!!");
 
          $stop;
 
          $stop;
 
        end
 
        end
 
    endcase
 
    endcase
 
  end
 
  end
 
endtask       // debug_cpu
 
endtask       // debug_cpu
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_cpu_set_addr;
 
task debug_cpu_wr_comm;
 
  input [2:0]   command;
 
  input [`DBG_CPU_ACC_TYPE_LEN -1:0]  acc_type;
 
  input [31:0]  addr;
 
  input [`DBG_CPU_ADR_LEN -1:0]       addr;
 
 
 
  input [`DBG_CPU_LEN_LEN -1:0]       length;
 
  input         gen_crc_err;
 
  input         gen_crc_err;
 
  integer i;
 
  integer i;
 
 
 
  reg   [`DBG_CPU_CMD_LEN -1:0]       command;
 
 
 
 
 
  begin
 
  begin
 
    $display("(%0t) Task debug_cpu_set_addr: ", $time);
 
    $display("(%0t) Task debug_cpu_wr_comm: ", $time);
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    command = `DBG_CPU_WR_COMM;
 
 
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(2);  // we are in shiftDR
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    calculate_crc(1'b0);
 
    calculate_crc(1'b0);
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
    for(i=2; i>=0; i=i-1)
 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      tdi_pad_i<=#1 command[i]; // command
 
      tdi_pad_i<=#1 command[i]; // command
 
      calculate_crc(command[i]);
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=31; i>=0; i=i-1)       // address
 
    for(i=`DBG_CPU_ACC_TYPE_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 acc_type[i]; // command
 
 
 
      calculate_crc(acc_type[i]);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_ADR_LEN -1; i>=0; i=i-1)       // address
 
    begin
 
    begin
 
      tdi_pad_i<=#1 addr[i];
 
      tdi_pad_i<=#1 addr[i];
 
      calculate_crc(addr[i]);
 
      calculate_crc(addr[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    for(i=31; i>=0; i=i-1)
 
    for(i=`DBG_CPU_LEN_LEN -1; i>=0; i=i-1)       // length
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 length[i];
 
 
 
      calculate_crc(length[i]);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
 
      else
 
      else
 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
Line 1390... Line 1486... 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
    gen_clk(`DBG_CPU_STATUS_LEN);   // Generating 4 clocks to read out status.
 
 
 
 
 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
 
 
 
      begin
 
 
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_cpu[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_cpu)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_cpu_wr_comm error: ", $time);
 
 
 
        casex (status_cpu)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("??? error !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
 
 
 
        endcase
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
 
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    begin
 
    begin
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to exit1_dr
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
    if (~crc_match_in)
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to update_dr
 
 
 
    tms_pad_i<=#1 1'b0;
 
 
 
    gen_clk(1);         // to run_test_idle
 
 
 
  end
 
 
 
endtask       // debug_cpu_wr_comm
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_cpu_wr_ctrl;
 
 
 
  input [`DBG_CPU_DR_LEN -1:0]  data;
 
 
 
  input [99:0]                  text;
 
 
 
  integer                       i;
 
 
 
  reg   [`DBG_CPU_CMD_LEN -1:0] command;
 
 
 
 
 
      begin
 
      begin
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
    test_text = text;
 
 
 
 
 
 
 
    $display("(%0t) Task debug_cpu_wr_ctrl (data=0x%0x (%0s))", $time, data, text);
 
 
 
 
 
 
 
    command = `DBG_CPU_WR_CTRL;
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);
 
 
 
    tms_pad_i<=#1 1'b0;
 
 
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
 
 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
 
 
    calculate_crc(1'b0);
 
 
 
    gen_clk(1);
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 command[i]; // command
 
 
 
      calculate_crc(command[i]);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 data[i];                                    // data (used cotrol bits
 
 
 
      calculate_crc(data[i]);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)  // unused control bits
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 1'b0;
 
 
 
      calculate_crc(1'b0);
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 crc_out[i];    // ok crc
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
 
 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
 
 
 
 
 
 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
 
 
 
      begin
 
 
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_cpu[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_cpu)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_cpu_wr_ctrl error: ", $time);
 
 
 
        casex (status_cpu)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("??? error !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("??? error !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("??? error !!!\n\n", $time);
 
 
 
        endcase
 
        $stop;
 
        $stop;
 
      end
 
      end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
 
 
    gen_clk(1);         // to update_dr
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    tms_pad_i<=#1 0;
 
    begin
 
    gen_clk(1);         // to run_test_idle
 
      gen_clk(1);
 
  end
 
  end
 
endtask       // debug_cpu_set_addr
 
 
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to update_dr
 
 
 
    tms_pad_i<=#1 1'b0;
 
 
 
    gen_clk(1);         // to run_test_idle
 
 
 
  end
 
 
 
endtask       // debug_cpu_wr_ctrl
 
 
 
 
 
 
 
 
 
task debug_cpu_go;
 
 
 
  input [2:0]   command;
 
 
 
  input [31:0]  data;
 
 
 
  input         gen_crc_err;
 
 
 
  integer i, len;
 
 
 
 
 
 
 
 
 
task debug_cpu_rd_ctrl;
 
 
 
  output [`DBG_CPU_CTRL_LEN -1:0] data;
 
 
 
  input  [99:0] text;
 
 
 
  integer                         i;
 
 
 
  reg   [`DBG_CPU_CMD_LEN -1:0]   command;
 
 
 
 
 
  begin
 
  begin
 
    $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
    test_text = text;
 
 
 
    $display("(%0t) Task debug_cpu_rd_ctrl: ", $time);
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    command = `DBG_CPU_RD_CTRL;
 
 
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(2);  // we are in shiftDR
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
    crc_out = 32'hffffffff; // Initialize outgoing CRC
 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
    calculate_crc(1'b0);
 
    calculate_crc(1'b0);
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
    for(i=2; i>=0; i=i-1)
 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
 
    begin
 
    begin
 
      tdi_pad_i<=#1 command[i]; // command
 
      tdi_pad_i<=#1 command[i]; // command
 
      calculate_crc(command[i]);
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 crc_out[i];
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
    if (last_wb_cmd == `CPU_WRITE32)
 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)     // data (used control bits)
 
      begin
 
      begin
 
        len = 31;
 
      gen_clk(1);
 
        $display("\t\tdata = 0x%x", data);
 
      data[i] = tdo;
 
      end
 
      end
 
    else if ((last_wb_cmd == `CPU_WRITE8) | (last_wb_cmd == `CPU_WRITE_REG))
 
 
 
 
 
    for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)       // unused control bits
 
      begin
 
      begin
 
        len = 7;
 
      gen_clk(1);
 
        $display("\t\tdata = 0x%x", data[7:0]);
 
 
 
      end
 
      end
 
    else
 
 
 
      len = 0;
 
 
 
 
 
 
 
    if (len>0)  // When CPU_WRITEx was previously activated, data needs to be shifted.
 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
 
      begin
 
      begin
 
        for (i=len; i>=0; i=i-1)
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_cpu[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_cpu)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_cpu_rd_ctrl: ", $time);
 
 
 
        casex (status_cpu)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Unknown command !!!\n\n", $time);
 
 
 
        endcase
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
 
 
 
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
          begin
 
          begin
 
            tdi_pad_i<=#1 data[i];
 
 
 
            calculate_crc(data[i]);
 
 
 
            gen_clk(1);
 
            gen_clk(1);
 
          end
 
          end
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);         // to update_dr
 
 
 
    tms_pad_i<=#1 1'b0;
 
 
 
    gen_clk(1);         // to run_test_idle
 
      end
 
      end
 
 
 
endtask       // debug_cpu_rd_ctrl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
task debug_cpu_go;
 
 
 
  input         wait_for_cpu_ready;
 
 
 
  input         gen_crc_err;
 
 
 
  integer i;
 
 
 
  reg   [4:0]   bit_pointer;
 
 
 
  integer       word_pointer;
 
 
 
  reg  [31:0]   tmp_data;
 
 
 
  reg [`DBG_CPU_CMD_LEN -1:0]       command;
 
 
 
 
 
 
 
 
 
    for(i=31; i>=0; i=i-1)
 
 
 
    begin
 
    begin
 
      if (gen_crc_err & (i==0))  // Generate crc error at last crc bit
 
    $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_cpu_cmd_text);
 
        tdi_pad_i<=#1 ~crc_out[i];   // error crc
 
    command = `DBG_CPU_GO;
 
      else
 
    word_pointer = 0;
 
        tdi_pad_i<=#1 crc_out[i];    // ok crc
 
 
 
 
 
 
 
 
 
    tms_pad_i<=#1 1'b1;
 
 
 
    gen_clk(1);
 
 
 
    tms_pad_i<=#1 1'b0;
 
 
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
 
 
    crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'b0; // module_select bit = 0
 
 
 
    calculate_crc(1'b0);
 
 
 
    gen_clk(1);
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 command[i]; // command
 
 
 
      calculate_crc(command[i]);
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
 
 
 
 
 
 
    crc_in = 32'hffffffff;  // Initialize incoming CRC
 
    if (last_cpu_cmd == `DBG_CPU_WRITE)  // When DBG_CPU_WRITE was previously activated, data needs to be shifted.
 
 
 
      begin
 
 
 
        for (i=0; i<((dbg_tb.i_dbg_top.i_dbg_cpu.len_var) << 3); i=i+1)
 
 
 
          begin
 
 
 
            tmp_data = wb_data[word_pointer];
 
 
 
            if ((!(i%32)) && (i>0))
 
 
 
              begin
 
 
 
                word_pointer = word_pointer + 1;
 
 
 
              end
 
 
 
            bit_pointer = 31-i[4:0];
 
 
 
            tdi_pad_i<=#1 tmp_data[bit_pointer];
 
 
 
            calculate_crc(tmp_data[bit_pointer]);
 
 
 
            gen_clk(1);
 
 
 
 
 
 
 
          end
 
 
 
      end
 
 
 
 
 
 
 
    for(i=`DBG_CPU_CRC_LEN -1; i>=1; i=i-1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 crc_out[i];
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    if (gen_crc_err)  // Generate crc error at last crc bit
 
 
 
      tdi_pad_i<=#1 ~crc_out[0];   // error crc
 
 
 
    else
 
 
 
      tdi_pad_i<=#1 crc_out[0];    // ok crc
 
 
 
 
 
 
 
    if (wait_for_cpu_ready)
 
 
 
      begin
 
 
 
        tms_pad_i<=#1 1'b1;
 
 
 
        gen_clk(1);       // to exit1_dr. Last CRC is shifted on this clk
 
 
 
        tms_pad_i<=#1 1'b0;
 
 
 
        gen_clk(1);       // to pause_dr
 
 
 
 
 
 
 
        #2;             // wait a bit for tdo to activate
 
 
 
        while (tdo)     // waiting for wb to send "ready"
 
 
 
        begin
 
 
 
          gen_clk(1);       // staying in pause_dr
 
 
 
        end
 
 
 
 
 
    if (last_wb_cmd == `CPU_READ32)
 
        tms_pad_i<=#1 1'b1;
 
      len = 32;
 
        gen_clk(1);       // to exit2_dr
 
    else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
 
        tms_pad_i<=#1 1'b0;
 
      len = 8;
 
        gen_clk(1);       // to shift_dr
 
 
 
      end
 
    else
 
    else
 
      len = 0;
 
      begin
 
 
 
        gen_clk(1);       // Last CRC is shifted on this clk
 
 
 
      end
 
 
 
 
 
 
 
 
 
 
 
    tdi_pad_i<=#1 1'hz;
 
 
 
    crc_in = {`DBG_CPU_CRC_LEN{1'b1}};  // Initialize incoming CRC to all ff
 
 
 
 
 
    if (len>0)    // When CPU_READx was previously activated, data needs to be shifted.
 
    if (last_cpu_cmd == `DBG_CPU_READ)  // When DBG_CPU_READ was previously activated, data needs to be shifted.
 
 
 
      begin
 
 
 
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_limit>>3);
 
 
 
        word_pointer = 0; // Reset pointer
 
 
 
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_limit); i=i+1)
 
      begin
 
      begin
 
        $display("\t\tGenerating %0d clocks to read out the data.", len);
 
 
 
        for (i=0; i<len; i=i+1)
 
 
 
          gen_clk(1);
 
          gen_clk(1);
 
 
 
            if (i[4:0] == 31)   // Latching data
 
 
 
              begin
 
 
 
                wb_data[word_pointer] = in_data_be;
 
 
 
                $display("\t\tin_data_be = 0x%x", in_data_be);
 
 
 
                word_pointer = word_pointer + 1;
 
 
 
              end
 
 
 
          end
 
      end
 
      end
 
 
 
 
 
 
 
 
 
    gen_clk(`DBG_CPU_STATUS_LEN);   // Generating 4 clocks to read out status.
 
    for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
 
 
 
      begin
 
 
 
        gen_clk(1);     // Generating clock to read out a status bit.
 
 
 
        status_cpu[i] = tdo;
 
 
 
      end
 
 
 
 
 
 
 
    if (|status_cpu)
 
 
 
      begin
 
 
 
        $write("(*E) (%0t) debug_cpu_go error: ", $time);
 
 
 
        casex (status_cpu)
 
 
 
          4'b1xxx : $display("CRC error !!!\n\n", $time);
 
 
 
          4'bx1xx : $display("Unknown command !!!\n\n", $time);
 
 
 
          4'bxx1x : $display("??? error !!!\n\n", $time);
 
 
 
          4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
 
 
 
        endcase
 
 
 
        $stop;
 
 
 
      end
 
 
 
 
 
 
 
 
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1)  // Getting in the CRC
 
    begin
 
    begin
 
      gen_clk(1);
 
      gen_clk(1);
 
    end
 
    end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to exit1_dr
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
    if (~crc_match_in)
 
    if (~crc_match_in)
 
      begin
 
      begin
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
        $display("(%0t) Incoming CRC failed !!!", $time);
 
        $stop;
 
        $stop;
 
      end
 
      end
 
 
 
 
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1'b1;
 
    gen_clk(1);         // to update_dr
 
    gen_clk(1);         // to update_dr
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 1'b0;
 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_cpu_go
 
endtask       // debug_cpu_go
 
`endif  // CPU_SUPPORTED
 
`endif  // DBG_CPU_SUPPORTED
 
 
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge tck_pad_i)
 
always @ (posedge tck_pad_i)
 
begin
 
begin
Line 1622... Line 1948... 
*                                                                                 *
 
*                                                                                 *
 
*   Printing the information to the screen                                        *
 
*   Printing the information to the screen                                        *
 
*                                                                                 *
 
*                                                                                 *
 
**********************************************************************************/
 
**********************************************************************************/
 
 
 
 
 
`ifdef MORE_DBG_INFO
 
`ifdef DBG_MORE_INFO
 
always @ (posedge tck_pad_i)
 
always @ (posedge tck_pad_i)
 
begin
 
begin
 
  if(dbg_tb.i_tap_top.update_ir)
 
  if(dbg_tb.i_tap_top.update_ir)
 
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
 
    case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
 
      `EXTEST         : $display("\tInstruction EXTEST entered");
 
      `EXTEST         : $display("\tInstruction EXTEST entered");
Line 1657... Line 1983... 
 
 
 
 
// Detecting CRC error
 
// Detecting CRC error
 
/*
 
/*
 
always @ (
 
always @ (
 
           posedge dbg_tb.i_dbg_top.module_latch_en
 
           posedge dbg_tb.i_dbg_top.module_latch_en
 
           `ifdef WISHBONE_SUPPORTED
 
           `ifdef DBG_WISHBONE_SUPPORTED
 
           or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
 
           or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
 
           `endif
 
           `endif
 
           `ifdef CPU_SUPPORTED
 
           `ifdef DBG_CPU_SUPPORTED
 
           or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
 
           or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
 
           `endif
 
           `endif
 
         )
 
         )
 
 
 
 
 
 
 
 

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