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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2003/12/23 14:26:01 mohor
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// New version of the debug interface. Not finished, yet.
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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| Line 95... |
Line 98... |
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/*------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------
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Maximum values for WAIT and RETRY counters and which response !!!
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Maximum values for WAIT and RETRY counters and which response !!!
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------------------------------------------------------------------------------------------------------*/
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------------------------------------------------------------------------------------------------------*/
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reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
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reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
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reg [7:0] wait_cyc;
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reg [8:0] wait_cyc;
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reg [7:0] max_retry;
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reg [7:0] max_retry;
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// assign registers to default state while in reset
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// assign registers to default state while in reset
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// always@(RST_I)
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// always@(RST_I)
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// begin
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// begin
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Line 114... |
// end
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// end
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// end //reset
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// end //reset
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task cycle_response;
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task cycle_response;
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input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
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input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
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input [7:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
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input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
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input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
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begin
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begin
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// assign values
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// assign values
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a_e_r_resp <= #1 ack_err_rty_resp;
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a_e_r_resp <= #1 ack_err_rty_resp;
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wait_cyc <= #1 wait_cycles;
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wait_cyc <= #1 wait_cycles;
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Line 204... |
retry_num = retry_cnt;
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retry_num = retry_cnt;
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retry_expired = 1'b1;
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retry_expired = 1'b1;
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end
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end
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end
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end
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reg [7:0] wait_cnt;
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reg [8:0] wait_cnt;
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reg [7:0] wait_num;
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reg [8:0] wait_num;
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reg wait_expired;
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reg wait_expired;
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// Wait counter
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// Wait counter
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always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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wait_cnt <= #1 8'h0;
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wait_cnt <= #1 9'h0;
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else
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else
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begin
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begin
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if (wait_expired || ~STB_I)
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if (wait_expired || ~STB_I)
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wait_cnt <= #1 8'h0;
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wait_cnt <= #1 9'h0;
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else
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else
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wait_cnt <= #1 wait_num;
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wait_cnt <= #1 wait_num;
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end
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end
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end
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end
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Line 277... |
end
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end
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end
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end
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else
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else
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if ((wait_cyc == 0) && (STB_I))
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if ((wait_cyc == 0) && (STB_I))
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begin
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begin
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wait_num = 8'h0;
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wait_num = 9'h0;
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wait_expired = 1'b1;
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wait_expired = 1'b1;
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if (a_e_r_resp == 3'b100)
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if (a_e_r_resp == 3'b100)
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begin
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begin
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calc_ack = 1'b1;
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calc_ack = 1'b1;
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calc_err = 1'b0;
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calc_err = 1'b0;
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Line 314... |
calc_rty = 1'b0;
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calc_rty = 1'b0;
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end
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end
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end
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end
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else
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else
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begin
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begin
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wait_num = 8'h0;
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wait_num = 9'h0;
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wait_expired = 1'b0;
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wait_expired = 1'b0;
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calc_ack = 1'b0;
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calc_ack = 1'b0;
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calc_err = 1'b0;
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calc_err = 1'b0;
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calc_rty = 1'b0;
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calc_rty = 1'b0;
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end
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end
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