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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu.v] - Diff between revs 108 and 121

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Rev 108	Rev 121
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2004/01/19 07:32:41 simons`
	`// Reset values width added because of FV, a good sentence changed because some tools can not handle it.`
	`//`
`// Revision 1.4 2004/01/17 18:38:11 mohor`	`// Revision 1.4 2004/01/17 18:38:11 mohor`
`// cpu_tall_o is set with cpu_stb_o or register.`	`// cpu_tall_o is set with cpu_stb_o or register.`
`//`	`//`
`// Revision 1.3 2004/01/17 18:01:24 mohor`	`// Revision 1.3 2004/01/17 18:01:24 mohor`
`// New version.`	`// New version.`
Line 164...	Line 167...
`reg write_cycle_reg;`	`reg write_cycle_reg;`
`reg write_cycle_cpu;`	`reg write_cycle_cpu;`
`wire read_cycle;`	`wire read_cycle;`
`wire write_cycle;`	`wire write_cycle;`

`reg [34:0] dr;`	`reg [31:0] dr;`
`wire [7:0] reg_data_out;`	`wire [7:0] reg_data_out;`

`wire dr_read_reg;`	`wire dr_read_reg;`
`wire dr_write_reg;`	`wire dr_write_reg;`
`wire dr_read_cpu8;`	`wire dr_read_cpu8;`
Line 191...	Line 194...
`reg cmd_write_cpu;`	`reg cmd_write_cpu;`
`reg cycle_32_bit;`	`reg cycle_32_bit;`
`reg reg_access;`	`reg reg_access;`

`reg [31:0] adr;`	`reg [31:0] adr;`
`reg set_addr;`
`reg cpu_ack_sync;`	`reg cpu_ack_sync;`
`reg cpu_ack_tck;`	`reg cpu_ack_tck;`
`reg cpu_ack_tck_q;`	`reg cpu_ack_tck_q;`
`reg cpu_stb;`	`reg cpu_stb;`
`reg cpu_stb_sync;`	`reg cpu_stb_sync;`
Line 340...	Line 342...




`// Latching address`	`// Latching address`
`always @ (posedge tck_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`
`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
`begin`
`if (~dr_go_latched)`
`begin`	`begin`
	`if (rst_i)`
	`adr <= #1 32'h0;`
	`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched))`
`adr <= #1 dr[31:0];`	`adr <= #1 dr[31:0];`
`set_addr <= #1 1'b1;`
`end`
`end`
`else`
`set_addr <= #1 1'b0;`
`end`	`end`


`assign cpu_addr_o = adr;`	`assign cpu_addr_o = adr;`


`// Shift register for shifting in and out the data`	`// Shift register for shifting in and out the data`
`always @ (posedge tck_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`
`if (reg_access)`
`begin`	`begin`
	`if (rst_i)`
	`dr <= #1 32'h0;`
	`else if (reg_access)`
`dr[31:24] <= #1 reg_data_out;`	`dr[31:24] <= #1 reg_data_out;`
`end`
`else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)`	`else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)`
`begin`	`begin`
`if (cycle_32_bit)`	`if (cycle_32_bit)`
`dr[31:0] <= #1 cpu_data_i;`	`dr[31:0] <= #1 cpu_data_i;`
`else`	`else`
`dr[31:24] <= #1 cpu_data_i[7:0];`	`dr[31:24] <= #1 cpu_data_i[7:0];`
`end`	`end`
`else if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle) \| (crc_cnt_end & (~data_cnt_end) & read_cycle)))`	`else if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle) \| (crc_cnt_end & (~data_cnt_end) & read_cycle)))`
`begin`	`begin`
`dr <= #1 {dr[33:0], tdi_i};`	`dr <= #1 {dr[30:0], tdi_i};`
`end`	`end`
`end`	`end`


assign dr_read_reg = dr[2:0] == `CPU_READ_REG;	assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
Line 487...	Line 483...
`else if (cmd_write_reg & go_prelim)`	`else if (cmd_write_reg & go_prelim)`
`write_cycle_reg <= #1 1'b1;`	`write_cycle_reg <= #1 1'b1;`
`end`	`end`


`always @ (posedge tck_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (update_dr_i)`	`if (rst_i)`
	`write_cycle_cpu <= #1 1'b0;`
	`else if (update_dr_i)`
`write_cycle_cpu <= #1 1'b0;`	`write_cycle_cpu <= #1 1'b0;`
`else if (cmd_write_cpu & go_prelim)`	`else if (cmd_write_cpu & go_prelim)`
`write_cycle_cpu <= #1 1'b1;`	`write_cycle_cpu <= #1 1'b1;`
`end`	`end`

Line 551...	Line 549...
`end`	`end`



`// Start cpu access cycle`	`// Start cpu access cycle`
`always @ (posedge tck_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (update_dr_i)`	`if (rst_i)`
`cpu_stb <= #1 1'b0;`	`cpu_stb <= #1 1'b0;`
`else if (cpu_ack_tck)`	`else if (update_dr_i \| cpu_ack_tck)`
`cpu_stb <= #1 1'b0;`	`cpu_stb <= #1 1'b0;`
`else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) \| read_cycle_cpu & (~read_cycle_cpu_q))`	`else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) \| read_cycle_cpu & (~read_cycle_cpu_q))`
`cpu_stb <= #1 1'b1;`	`cpu_stb <= #1 1'b1;`
`end`	`end`

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu.v] - Diff between revs 108 and 121