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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2004/03/28 20:27:01 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// Revision 1.7 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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// All flipflops are reset.
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//
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//
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// Revision 1.6 2004/01/22 13:58:53 mohor
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// Revision 1.6 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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// Port signals are all set to zero after reset.
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| Line 150... |
Line 153... |
reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
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reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
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wire crc_cnt_end;
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wire crc_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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reg data_cnt_en;
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reg data_cnt_en;
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reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
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reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
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reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt_limit;
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reg [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
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wire data_cnt_end;
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wire data_cnt_end;
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reg data_cnt_end_q;
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reg data_cnt_end_q;
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reg crc_match_reg;
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reg crc_match_reg;
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reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
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reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
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| Line 384... |
Line 387... |
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// Upper limit. Data counter counts until this value is reached.
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// Upper limit. Data counter counts until this value is reached.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt_limit <= #1 {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
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data_cnt_limit <= #1 {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt_limit <= #1 {len + 1'b1, 3'b000};
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data_cnt_limit <= #1 len + 1'b1;
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end
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end
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
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begin
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begin
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| Line 423... |
Line 426... |
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assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
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assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
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assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
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assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
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assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
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assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
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assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
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assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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| Line 456... |
Line 459... |
else if (status_cnt_en)
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else if (status_cnt_en)
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status_cnt <= #1 status_cnt + 1'b1;
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status_cnt <= #1 status_cnt + 1'b1;
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end
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end
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or data_cnt_end or addr_len_cnt_end)
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always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
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curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
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acc_type_read or data_cnt_end or addr_len_cnt_end)
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begin
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begin
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if (enable && (!status_cnt_end))
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if (enable && (!status_cnt_end))
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begin
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begin
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if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
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if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
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status_cnt_en = 1'b1;
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status_cnt_en = 1'b1;
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