| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2004/04/07 19:28:55 igorm
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// Zero is shifted out when CTRL_READ command is active.
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//
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// Revision 1.10 2004/04/01 10:22:45 igorm
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// Revision 1.10 2004/04/01 10:22:45 igorm
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// Signals for easier debugging removed.
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// Signals for easier debugging removed.
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//
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//
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// Revision 1.9 2004/03/31 14:34:09 igorm
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// Revision 1.9 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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// data_cnt_lim length changed to reduce number of warnings.
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| Line 251... |
Line 254... |
latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
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dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
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end
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end
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else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
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else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
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begin
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begin
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dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
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dr[`DBG_CPU_DR_LEN -1:0] <= #1 {acc_type, adr, len};
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end
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end
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else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
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else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
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begin
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begin
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dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN] <= #1 ctrl_reg;
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dr[`DBG_CPU_DR_LEN -1:0] <= #1 {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
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end
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
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else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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| Line 884... |
Line 887... |
end
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end
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
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begin
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begin
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tdo_o = ~crc_match_reg;
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tdo_o = ~crc_match_reg;
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end
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end
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else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
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else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
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begin
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begin
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tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
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tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
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end
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end
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else if (curr_cmd_rd_ctrl && crc_cnt_end && (!addr_len_cnt_end))
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begin
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tdo_o = 1'b0;
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end
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else if (status_cnt_en)
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else if (status_cnt_en)
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begin
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begin
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tdo_o = status[3];
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tdo_o = status[3];
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end
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end
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else
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else
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