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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_cpu_defines.v ////
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//// dbg_cpu_defines.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Revision 1.2 2004/01/17 17:01:14 mohor
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// Almost finished.
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// Almost finished.
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//
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//
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// Revision 1.1 2004/01/16 14:53:33 mohor
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// Revision 1.1 2004/01/16 14:53:33 mohor
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// *** empty log message ***
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// *** empty log message ***
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//
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//
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//
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//
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//
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//
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// Defining commands for cpu module
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//`define CPU_STATUS 3'h0
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`define CPU_WRITE8 3'h1
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`define CPU_WRITE32 3'h2
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`define CPU_WRITE_REG 3'h3
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`define CPU_GO 3'h4
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`define CPU_READ8 3'h5
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`define CPU_READ32 3'h6
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`define CPU_READ_REG 3'h7
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// Defining length of the command
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`define DBG_CPU_CMD_LEN 3'd4
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`define DBG_CPU_CMD_CNT_WIDTH 3
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// Defining length of the access_type field
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`define DBG_CPU_ACC_TYPE_LEN 3'd4
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// Defining length of the address
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`define DBG_CPU_ADR_LEN 6'd32
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// Number of supported cpus
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// Defining length of the length register
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`define CPU_NUM 2
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`define DBG_CPU_LEN_LEN 5'd16
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// Defining total length of the DR needed
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// Registers addresses
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`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
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`define CPU_OP_ADR 2'd0
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`define CPU_SEL_ADR 2'd1
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// Defining length of the CRC
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// Defining length of the CRC
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`define DBG_CPU_CRC_LEN 32
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`define DBG_CPU_CRC_LEN 6'd32
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`define DBG_CPU_CRC_CNT_WIDTH 6
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// Defining length of status
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`define DBG_CPU_STATUS_LEN 3'd4
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`define DBG_CPU_STATUS_CNT_WIDTH 3
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// Defining length of the data
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`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3)
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// Defining length of the control register
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`define DBG_CPU_CTRL_LEN 2
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//Defining commands
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`define DBG_CPU_GO 4'h0
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`define DBG_CPU_RD_COMM 4'h1
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`define DBG_CPU_WR_COMM 4'h2
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`define DBG_CPU_WR_CTRL 4'h3
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`define DBG_CPU_RD_CTRL 4'h4
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// Defining access types for wishbone
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`define DBG_CPU_WRITE 4'h2
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`define DBG_CPU_READ 4'h6
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// Defining length of the status
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`define DBG_CPU_STATUS_LEN 4
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No newline at end of file
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No newline at end of file
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