URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Diff between revs 139 and 141

Rev 139	Rev 141
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2004/03/28 20:27:02 igorm`
	`// New release of the debug interface (3rd. release).`
	`//`
`// Revision 1.3 2004/03/22 16:35:46 igorm`	`// Revision 1.3 2004/03/22 16:35:46 igorm`
`// Temp version before changing dbg interface.`	`// Temp version before changing dbg interface.`
`//`	`//`
`// Revision 1.2 2004/01/17 17:01:14 mohor`	`// Revision 1.2 2004/01/17 17:01:14 mohor`
`// Almost finished.`	`// Almost finished.`
Line 81...	Line 84...
`define DBG_CPU_STATUS_LEN 3'd4	`define DBG_CPU_STATUS_LEN 3'd4
`define DBG_CPU_STATUS_CNT_WIDTH 3	`define DBG_CPU_STATUS_CNT_WIDTH 3

`// Defining length of the data`	`// Defining length of the data`
`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3)	`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3)
	`define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN

`// Defining length of the control register`	`// Defining length of the control register`
`define DBG_CPU_CTRL_LEN 2	`define DBG_CPU_CTRL_LEN 2

`//Defining commands`	`//Defining commands`