URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_cpu_defines.v] - Diff between revs 141 and 147

Rev 141	Rev 147
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2004/03/31 14:34:09 igorm`
	`// data_cnt_lim length changed to reduce number of warnings.`
	`//`
`// Revision 1.4 2004/03/28 20:27:02 igorm`	`// Revision 1.4 2004/03/28 20:27:02 igorm`
`// New release of the debug interface (3rd. release).`	`// New release of the debug interface (3rd. release).`
`//`	`//`
`// Revision 1.3 2004/03/22 16:35:46 igorm`	`// Revision 1.3 2004/03/22 16:35:46 igorm`
`// Temp version before changing dbg interface.`	`// Temp version before changing dbg interface.`
Line 93...	Line 96...

`//Defining commands`	`//Defining commands`
`define DBG_CPU_GO 4'h0	`define DBG_CPU_GO 4'h0
`define DBG_CPU_RD_COMM 4'h1	`define DBG_CPU_RD_COMM 4'h1
`define DBG_CPU_WR_COMM 4'h2	`define DBG_CPU_WR_COMM 4'h2
`define DBG_CPU_WR_CTRL 4'h3	`define DBG_CPU_RD_CTRL 4'h3
`define DBG_CPU_RD_CTRL 4'h4	`define DBG_CPU_WR_CTRL 4'h4

`// Defining access types for wishbone`	`// Defining access types for wishbone`
`define DBG_CPU_WRITE 4'h2	`define DBG_CPU_WRITE 4'h2
`define DBG_CPU_READ 4'h6	`define DBG_CPU_READ 4'h6