URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 11 and 12

Rev 11	Rev 12
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2001/09/24 14:06:42 mohor`
	`// Changes connected to the OpenRISC access (SPR read, SPR write).`
	`//`
`// Revision 1.3 2001/09/20 10:11:25 mohor`	`// Revision 1.3 2001/09/20 10:11:25 mohor`
`// Working version. Few bugs fixed, comments added.`	`// Working version. Few bugs fixed, comments added.`
`//`	`//`
`// Revision 1.2 2001/09/18 14:13:47 mohor`	`// Revision 1.2 2001/09/18 14:13:47 mohor`
`// Trace fixed. Some registers changed, trace simplified.`	`// Trace fixed. Some registers changed, trace simplified.`
Line 126...	Line 129...
`define GLOBAL_BS_CHAIN 4'b0000	`define GLOBAL_BS_CHAIN 4'b0000
`define RISC_DEBUG_CHAIN 4'b0001	`define RISC_DEBUG_CHAIN 4'b0001
`define RISC_TEST_CHAIN 4'b0010	`define RISC_TEST_CHAIN 4'b0010
`define TRACE_TEST_CHAIN 4'b0011	`define TRACE_TEST_CHAIN 4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100	`define REGISTER_SCAN_CHAIN 4'b0100
	`define WISHBONE_SCAN_CHAIN 4'b0101

`// Registers addresses`	`// Registers addresses`
`define MODER_ADR 5'h00	`define MODER_ADR 5'h00
`define TSEL_ADR 5'h01	`define TSEL_ADR 5'h01
`define QSEL_ADR 5'h02	`define QSEL_ADR 5'h02