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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 138 and 139

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  dbg_defines.v                                               ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.18  2004/03/22 16:35:46  igorm
 
// Temp version before changing dbg interface.
 
//
// Revision 1.17  2004/01/30 10:24:30  mohor
// Revision 1.17  2004/01/30 10:24:30  mohor
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
// turned on.
// turned on.
//
//
// Revision 1.16  2004/01/20 14:23:45  mohor
// Revision 1.16  2004/01/20 14:23:45  mohor
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//
//
//
//
 
 
 
 
// Length of the MODULE ID register
// Length of the MODULE ID register
`define MODULE_ID_LENGTH        4
`define DBG_TOP_MODULE_ID_LENGTH        4
 
 
// Length of data
// Length of data
`define MODULE_DATA_LEN  `MODULE_ID_LENGTH + 1
`define DBG_TOP_MODULE_DATA_LEN  `DBG_TOP_MODULE_ID_LENGTH + 1
`define DATA_CNT        3
`define DBG_TOP_DATA_CNT          3
 
 
// Length of status
// Length of status
`define DBG_TOP_STATUS_LEN          3'd4
`define DBG_TOP_STATUS_LEN          3'd4
`define DBG_TOP_STATUS_CNT_WIDTH    3
`define DBG_TOP_STATUS_CNT_WIDTH    3
 
 
// Length of the CRC
// Length of the CRC
`define DBG_TOP_CRC_LEN             32
`define DBG_TOP_CRC_LEN             32
`define CRC_CNT         6
`define DBG_TOP_CRC_CNT           6
 
 
// Chains
// Chains
`define CPU_DEBUG_MODULE      4'b0000
`define DBG_TOP_CPU_DEBUG_MODULE      4'b0000
`define WISHBONE_DEBUG_MODULE 4'b0001
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'b0001
 
 
// If WISHBONE debugging is supported uncomment the folowing line
// If WISHBONE debugging is supported uncomment the folowing line
`define WISHBONE_SUPPORTED
`define DBG_WISHBONE_SUPPORTED
 
 
// If CPU_DEBUG is supported uncomment the folowing line
// If CPU_DEBUG is supported uncomment the folowing line
`define CPU_SUPPORTED
`define DBG_CPU_SUPPORTED
 
 
// If more debug info is needed, uncomment the follofing line
// If more debug info is needed, uncomment the follofing line
//`define MORE_DBG_INFO
//`define DBG_MORE_INFO
 
 
 
 
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