URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 99 and 101

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Rev 99	Rev 101
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.36 2004/01/16 14:51:33 mohor`
	`// cpu registers added.`
	`//`
`// Revision 1.35 2004/01/14 22:59:16 mohor`	`// Revision 1.35 2004/01/14 22:59:16 mohor`
`// Temp version.`	`// Temp version.`
`//`	`//`
`// Revision 1.34 2003/12/23 15:07:34 mohor`	`// Revision 1.34 2003/12/23 15:07:34 mohor`
`// New directory structure. New version of the debug interface.`	`// New directory structure. New version of the debug interface.`
Line 170...	Line 173...

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
`include "dbg_defines.v"	`include "dbg_defines.v"
	`include "dbg_cpu_defines.v"

`// Top module`	`// Top module`
`module dbg_top(`	`module dbg_top(`
`// JTAG signals`	`// JTAG signals`
`tck_i,`	`tck_i,`
Line 187...	Line 191...

`// Instructions`	`// Instructions`
`debug_select_i,`	`debug_select_i,`

`// WISHBONE common signals`	`// WISHBONE common signals`
`wb_rst_i, wb_clk_i,`	`wb_rst_i,`
	`wb_clk_i,`

`// WISHBONE master interface`	`// WISHBONE master interface`
`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`	`wb_adr_o,`
`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`	`wb_dat_o,`
	`wb_dat_i,`
	`wb_cyc_o,`
	`wb_stb_o,`
	`wb_sel_o,`
	`wb_we_o,`
	`wb_ack_i,`
	`wb_cab_o,`
	`wb_err_i,`
	`wb_cti_o,`
	`wb_bte_o,`

	`// CPU signals`
	`cpu_clk_i,`
	`cpu_addr_o,`
	`cpu_data_i,`
	`cpu_data_o,`
	`cpu_bp_i,`
	`cpu_stall_o,`
	`cpu_stall_all_o,`
	`cpu_stb_o,`
	`cpu_sel_o,`
	`cpu_we_o,`
	`cpu_ack_i,`
	`cpu_rst_o`
`);`	`);`


`// JTAG signals`	`// JTAG signals`
`input tck_i;`	`input tck_i;`
Line 226...	Line 255...
`output wb_cab_o;`	`output wb_cab_o;`
`input wb_err_i;`	`input wb_err_i;`
`output [2:0] wb_cti_o;`	`output [2:0] wb_cti_o;`
`output [1:0] wb_bte_o;`	`output [1:0] wb_bte_o;`

	`// CPU signals`
	`input cpu_clk_i;`
	`output [31:0] cpu_addr_o;`
	`input [31:0] cpu_data_i;`
	`output [31:0] cpu_data_o;`
	`input cpu_bp_i;`
	`output cpu_stall_o;`
	`output cpu_stall_all_o;`
	`output cpu_stb_o;`
	output [`CPU_NUM -1:0] cpu_sel_o;
	`output cpu_we_o;`
	`input cpu_ack_i;`
	`output cpu_rst_o;`

`reg cpu_debug_scan_chain;`	`reg cpu_debug_scan_chain;`
`reg wishbone_scan_chain;`	`reg wishbone_scan_chain;`

reg [`DATA_CNT -1:0] data_cnt;	reg [`DATA_CNT -1:0] data_cnt;
Line 559...	Line 601...
`.cpu_ce_i (cpu_ce),`	`.cpu_ce_i (cpu_ce),`
`.crc_match_i (crc_match),`	`.crc_match_i (crc_match),`
`.crc_en_o (crc_en_cpu),`	`.crc_en_o (crc_en_cpu),`
`.shift_crc_o (shift_crc_cpu),`	`.shift_crc_o (shift_crc_cpu),`
`.rst_i (wb_rst_i),`	`.rst_i (wb_rst_i),`
`.clk_i (wb_clk_i)`
	`// CPU signals`
	`.cpu_clk_i (cpu_clk_i),`
	`.cpu_addr_o (cpu_addr_o),`
	`.cpu_data_i (cpu_data_i),`
	`.cpu_data_o (cpu_data_o),`
	`.cpu_bp_i (cpu_bp_i),`
	`.cpu_stall_o (cpu_stall_o),`
	`.cpu_stall_all_o (cpu_stall_all_o),`
	`.cpu_stb_o (cpu_stb_o),`
	`.cpu_sel_o (cpu_sel_o),`
	`.cpu_we_o (cpu_we_o),`
	`.cpu_ack_i (cpu_ack_i),`
	`.cpu_rst_o (cpu_rst_o)`


`);`	`);`


`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 99 and 101