URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 101 and 106

Rev 101	Rev 106
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.37 2004/01/17 17:01:14 mohor`
	`// Almost finished.`
	`//`
`// Revision 1.36 2004/01/16 14:51:33 mohor`	`// Revision 1.36 2004/01/16 14:51:33 mohor`
`// cpu registers added.`	`// cpu registers added.`
`//`	`//`
`// Revision 1.35 2004/01/14 22:59:16 mohor`	`// Revision 1.35 2004/01/14 22:59:16 mohor`
`// Temp version.`	`// Temp version.`
Line 497...	Line 500...



`assign shift_crc = shift_crc_wb \| shift_crc_cpu;`	`assign shift_crc = shift_crc_wb \| shift_crc_cpu;`

`always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select)`	`always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select or cpu_ce)`
`begin`	`begin`
`if (shift_crc) // shifting crc`	`if (shift_crc) // shifting crc`
`tdo_tmp = crc_out;`	`tdo_tmp = crc_out;`
`else if (wishbone_ce) // shifting data from wb`	`else if (wishbone_ce) // shifting data from wb`
`tdo_tmp = tdo_wb;`	`tdo_tmp = tdo_wb;`