OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 106 and 108

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 106 Rev 108
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.38  2004/01/18 09:22:47  simons
 
// Sensitivity list updated.
 
//
// Revision 1.37  2004/01/17 17:01:14  mohor
// Revision 1.37  2004/01/17 17:01:14  mohor
// Almost finished.
// Almost finished.
//
//
// Revision 1.36  2004/01/16 14:51:33  mohor
// Revision 1.36  2004/01/16 14:51:33  mohor
// cpu registers added.
// cpu registers added.
Line 316... Line 319...
 
 
// data counter
// data counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge wb_rst_i)
begin
begin
  if (wb_rst_i)
  if (wb_rst_i)
    data_cnt <= #1 'h0;
    data_cnt <= #1 {`DATA_CNT{1'b0}};
  else if(shift_dr_i & (~data_cnt_end))
  else if(shift_dr_i & (~data_cnt_end))
    data_cnt <= #1 data_cnt + 1'b1;
    data_cnt <= #1 data_cnt + 1'b1;
  else if (update_dr_i)
  else if (update_dr_i)
    data_cnt <= #1 'h0;
    data_cnt <= #1 {`DATA_CNT{1'b0}};
end
end
 
 
 
 
assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
 
 
 
 
// crc counter
// crc counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge wb_rst_i)
begin
begin
  if (wb_rst_i)
  if (wb_rst_i)
    crc_cnt <= #1 'h0;
    crc_cnt <= #1 {`CRC_CNT{1'b0}};
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
    crc_cnt <= #1 crc_cnt + 1'b1;
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
    crc_cnt <= #1 {`CRC_CNT{1'b0}};
end
end
 
 
assign crc_cnt_end = crc_cnt == `CRC_LEN;
assign crc_cnt_end = crc_cnt == `CRC_LEN;
 
 
 
 
Line 353... Line 356...
 
 
// status counter
// status counter
always @ (posedge tck_i or posedge wb_rst_i)
always @ (posedge tck_i or posedge wb_rst_i)
begin
begin
  if (wb_rst_i)
  if (wb_rst_i)
    status_cnt <= #1 'h0;
    status_cnt <= #1 {`STATUS_CNT{1'b0}};
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
  else if (update_dr_i)
    status_cnt <= #1 'h0;
    status_cnt <= #1 {`STATUS_CNT{1'b0}};
end
end
 
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
assign status_cnt_end = status_cnt == `STATUS_LEN;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.