URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 123 and 128

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 123	Rev 128
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.41 2004/01/25 14:04:18 mohor`
	`// All flipflops are reset.`
	`//`
`// Revision 1.40 2004/01/20 14:23:47 mohor`	`// Revision 1.40 2004/01/20 14:23:47 mohor`
`// Define name changed.`	`// Define name changed.`
`//`	`//`
`// Revision 1.39 2004/01/19 07:32:41 simons`	`// Revision 1.39 2004/01/19 07:32:41 simons`
`// Reset values width added because of FV, a good sentence changed because some tools can not handle it.`	`// Reset values width added because of FV, a good sentence changed because some tools can not handle it.`
Line 193...	Line 196...
`module dbg_top(`	`module dbg_top(`
`// JTAG signals`	`// JTAG signals`
`tck_i,`	`tck_i,`
`tdi_i,`	`tdi_i,`
`tdo_o,`	`tdo_o,`
	`rst_i,`

`// TAP states`	`// TAP states`
`shift_dr_i,`	`shift_dr_i,`
`pause_dr_i,`	`pause_dr_i,`
`update_dr_i,`	`update_dr_i,`

`// Instructions`	`// Instructions`
`debug_select_i,`	`debug_select_i`


	`ifdef WISHBONE_SUPPORTED
`// WISHBONE common signals`	`// WISHBONE common signals`
`wb_rst_i,`	`,`
`wb_clk_i,`	`wb_clk_i,`

`// WISHBONE master interface`	`// WISHBONE master interface`
`wb_adr_o,`	`wb_adr_o,`
`wb_dat_o,`	`wb_dat_o,`
Line 218...	Line 224...
`wb_we_o,`	`wb_we_o,`
`wb_ack_i,`	`wb_ack_i,`
`wb_cab_o,`	`wb_cab_o,`
`wb_err_i,`	`wb_err_i,`
`wb_cti_o,`	`wb_cti_o,`
`wb_bte_o,`	`wb_bte_o`
	`endif

	`ifdef CPU_SUPPORTED
`// CPU signals`	`// CPU signals`
	`,`
`cpu_clk_i,`	`cpu_clk_i,`
`cpu_addr_o,`	`cpu_addr_o,`
`cpu_data_i,`	`cpu_data_i,`
`cpu_data_o,`	`cpu_data_o,`
`cpu_bp_i,`	`cpu_bp_i,`
Line 233...	Line 242...
`cpu_stb_o,`	`cpu_stb_o,`
`cpu_sel_o,`	`cpu_sel_o,`
`cpu_we_o,`	`cpu_we_o,`
`cpu_ack_i,`	`cpu_ack_i,`
`cpu_rst_o`	`cpu_rst_o`
	`endif
`);`	`);`


`// JTAG signals`	`// JTAG signals`
`input tck_i;`	`input tck_i;`
`input tdi_i;`	`input tdi_i;`
`output tdo_o;`	`output tdo_o;`
	`input rst_i;`

`// TAP states`	`// TAP states`
`input shift_dr_i;`	`input shift_dr_i;`
`input pause_dr_i;`	`input pause_dr_i;`
`input update_dr_i;`	`input update_dr_i;`

`// Instructions`	`// Instructions`
`input debug_select_i;`	`input debug_select_i;`

`// WISHBONE common signals`	`ifdef WISHBONE_SUPPORTED
`input wb_rst_i; // WISHBONE reset`	`input wb_clk_i;`
`input wb_clk_i; // WISHBONE clock`

`// WISHBONE master interface`
`output [31:0] wb_adr_o;`	`output [31:0] wb_adr_o;`
`output [31:0] wb_dat_o;`	`output [31:0] wb_dat_o;`
`input [31:0] wb_dat_i;`	`input [31:0] wb_dat_i;`
`output wb_cyc_o;`	`output wb_cyc_o;`
`output wb_stb_o;`	`output wb_stb_o;`
Line 267...	Line 275...
`output wb_cab_o;`	`output wb_cab_o;`
`input wb_err_i;`	`input wb_err_i;`
`output [2:0] wb_cti_o;`	`output [2:0] wb_cti_o;`
`output [1:0] wb_bte_o;`	`output [1:0] wb_bte_o;`

	`reg wishbone_scan_chain;`
	`reg wishbone_ce;`
	`wire tdi_wb;`
	`wire tdo_wb;`
	`wire crc_en_wb;`
	`wire shift_crc_wb;`
	`else
	`wire crc_en_wb = 1'b0;`
	`wire shift_crc_wb = 1'b0;`
	`endif

	`ifdef CPU_SUPPORTED
`// CPU signals`	`// CPU signals`
`input cpu_clk_i;`	`input cpu_clk_i;`
`output [31:0] cpu_addr_o;`	`output [31:0] cpu_addr_o;`
`input [31:0] cpu_data_i;`	`input [31:0] cpu_data_i;`
`output [31:0] cpu_data_o;`	`output [31:0] cpu_data_o;`
Line 282...	Line 302...
`output cpu_we_o;`	`output cpu_we_o;`
`input cpu_ack_i;`	`input cpu_ack_i;`
`output cpu_rst_o;`	`output cpu_rst_o;`

`reg cpu_debug_scan_chain;`	`reg cpu_debug_scan_chain;`
`reg wishbone_scan_chain;`	`reg cpu_ce;`
	`wire tdi_cpu;`
	`wire tdo_cpu;`
	`wire crc_en_cpu;`
	`wire shift_crc_cpu;`
	`else
	`wire crc_en_cpu = 1'b0;`
	`wire shift_crc_cpu = 1'b0;`
	`endif


reg [`DATA_CNT -1:0] data_cnt;	reg [`DATA_CNT -1:0] data_cnt;
reg [`CRC_CNT -1:0] crc_cnt;	reg [`CRC_CNT -1:0] crc_cnt;
reg [`STATUS_CNT -1:0] status_cnt;	reg [`STATUS_CNT -1:0] status_cnt;
reg [`CHAIN_DATA_LEN -1:0] chain_dr;	reg [`CHAIN_DATA_LEN -1:0] chain_dr;
Line 299...	Line 328...
`reg crc_cnt_end_q;`	`reg crc_cnt_end_q;`
`reg chain_select;`	`reg chain_select;`
`reg chain_select_error;`	`reg chain_select_error;`
`wire crc_out;`	`wire crc_out;`
`wire crc_match;`	`wire crc_match;`
`wire crc_en_wb;`
`wire crc_en_cpu;`
`wire shift_crc_wb;`
`wire shift_crc_cpu;`

`wire data_shift_en;`	`wire data_shift_en;`
`wire selecting_command;`	`wire selecting_command;`

`reg tdo_o;`	`reg tdo_o;`
`reg wishbone_ce;`
`reg cpu_ce;`

`wire tdi_wb;`
`wire tdi_cpu;`

`wire tdo_wb;`
`wire tdo_cpu;`

`wire shift_crc;`	`wire shift_crc;`

`// data counter`	`// data counter`
`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
data_cnt <= #1 {`DATA_CNT{1'b0}};	data_cnt <= #1 {`DATA_CNT{1'b0}};
`else if(shift_dr_i & (~data_cnt_end))`	`else if(shift_dr_i & (~data_cnt_end))`
`data_cnt <= #1 data_cnt + 1'b1;`	`data_cnt <= #1 data_cnt + 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
data_cnt <= #1 {`DATA_CNT{1'b0}};	data_cnt <= #1 {`DATA_CNT{1'b0}};
Line 335...	Line 355...

assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;	assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;


`// crc counter`	`// crc counter`
`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
crc_cnt <= #1 {`CRC_CNT{1'b0}};	crc_cnt <= #1 {`CRC_CNT{1'b0}};
`else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)`	`else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)`
`crc_cnt <= #1 crc_cnt + 1'b1;`	`crc_cnt <= #1 crc_cnt + 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
crc_cnt <= #1 {`CRC_CNT{1'b0}};	crc_cnt <= #1 {`CRC_CNT{1'b0}};
`end`	`end`

assign crc_cnt_end = crc_cnt == `CRC_LEN;	assign crc_cnt_end = crc_cnt == `CRC_LEN;


`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
`crc_cnt_end_q <= #1 1'b0;`	`crc_cnt_end_q <= #1 1'b0;`
`else`	`else`
`crc_cnt_end_q <= #1 crc_cnt_end;`	`crc_cnt_end_q <= #1 crc_cnt_end;`
`end`	`end`


`// status counter`	`// status counter`
`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
status_cnt <= #1 {`STATUS_CNT{1'b0}};	status_cnt <= #1 {`STATUS_CNT{1'b0}};
`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`	`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
`status_cnt <= #1 status_cnt + 1'b1;`	`status_cnt <= #1 status_cnt + 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
status_cnt <= #1 {`STATUS_CNT{1'b0}};	status_cnt <= #1 {`STATUS_CNT{1'b0}};
Line 374...	Line 394...


assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;	assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;


`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
`chain_select <= #1 1'b0;`	`chain_select <= #1 1'b0;`
`else if(selecting_command & tdi_i) // Chain select`	`else if(selecting_command & tdi_i) // Chain select`
`chain_select <= #1 1'b1;`	`chain_select <= #1 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
`chain_select <= #1 1'b0;`	`chain_select <= #1 1'b0;`
`end`	`end`


`always @ (chain)`	`always @ (chain)`
`begin`	`begin`
	`ifdef CPU_SUPPORTED
`cpu_debug_scan_chain <= #1 1'b0;`	`cpu_debug_scan_chain <= #1 1'b0;`
	`endif
	`ifdef WISHBONE_SUPPORTED
`wishbone_scan_chain <= #1 1'b0;`	`wishbone_scan_chain <= #1 1'b0;`
	`endif
`chain_select_error <= #1 1'b0;`	`chain_select_error <= #1 1'b0;`

`case (chain) /* synthesis parallel_case */`	`case (chain) /* synthesis parallel_case */`
	`ifdef CPU_SUPPORTED
`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;	`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;
	`endif
	`ifdef WISHBONE_SUPPORTED
`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1;	`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1;
	`endif
`default : chain_select_error <= #1 1'b1;`	`default : chain_select_error <= #1 1'b1;`
`endcase`	`endcase`
`end`	`end`


`assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q);`	`assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q);`


`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
chain <= `CHAIN_ID_LENGTH'b111;	chain <= `CHAIN_ID_LENGTH'b111;
`else if(chain_latch_en & crc_match)`	`else if(chain_latch_en & crc_match)`
chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];	chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
`end`	`end`


`assign data_shift_en = shift_dr_i & (~data_cnt_end);`	`assign data_shift_en = shift_dr_i & (~data_cnt_end);`


`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
chain_dr <= #1 `CHAIN_DATA_LEN'h0;	chain_dr <= #1 `CHAIN_DATA_LEN'h0;
`else if (data_shift_en)`	`else if (data_shift_en)`
chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};	chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};
`end`	`end`

Line 429...	Line 457...
`dbg_crc32_d1 i_dbg_crc32_d1_in`	`dbg_crc32_d1 i_dbg_crc32_d1_in`
`(`	`(`
`.data (tdi_i),`	`.data (tdi_i),`
`.enable (shift_dr_i),`	`.enable (shift_dr_i),`
`.shift (1'b0),`	`.shift (1'b0),`
`.rst (wb_rst_i),`	`.rst (rst_i),`
`.sync_rst (update_dr_i),`	`.sync_rst (update_dr_i),`
`.crc_out (),`	`.crc_out (),`
`.clk (tck_i),`	`.clk (tck_i),`
`.crc_match (crc_match)`	`.crc_match (crc_match)`
`);`	`);`
Line 441...	Line 469...

`reg tdo_chain_select;`	`reg tdo_chain_select;`
`wire crc_en;`	`wire crc_en;`
`wire crc_en_dbg;`	`wire crc_en_dbg;`
`reg crc_started;`	`reg crc_started;`

`assign crc_en = crc_en_dbg \| crc_en_wb \| crc_en_cpu;`	`assign crc_en = crc_en_dbg \| crc_en_wb \| crc_en_cpu;`

`assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);`	`assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);`

`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
`crc_started <= #1 1'b0;`	`crc_started <= #1 1'b0;`
`else if (crc_en)`	`else if (crc_en)`
`crc_started <= #1 1'b1;`	`crc_started <= #1 1'b1;`
`else if (update_dr_i)`	`else if (update_dr_i)`
`crc_started <= #1 1'b0;`	`crc_started <= #1 1'b0;`
Line 465...	Line 495...
`(`	`(`
`.data (tdo_tmp),`	`.data (tdo_tmp),`
`.enable (crc_en), // enable has priority`	`.enable (crc_en), // enable has priority`
`// .shift (1'b0),`	`// .shift (1'b0),`
`.shift (shift_dr_i & crc_started & (~crc_en)),`	`.shift (shift_dr_i & crc_started & (~crc_en)),`
`.rst (wb_rst_i),`	`.rst (rst_i),`
`.sync_rst (update_dr_i),`	`.sync_rst (update_dr_i),`
`.crc_out (crc_out),`	`.crc_out (crc_out),`
`.clk (tck_i),`	`.clk (tck_i),`
`.crc_match ()`	`.crc_match ()`
`);`	`);`
Line 512...	Line 542...



`assign shift_crc = shift_crc_wb \| shift_crc_cpu;`	`assign shift_crc = shift_crc_wb \| shift_crc_cpu;`

`always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select or cpu_ce)`	`always @ (shift_crc or crc_out or tdo_chain_select`
	`ifdef WISHBONE_SUPPORTED
	`or wishbone_ce or tdo_wb`
	`endif
	`ifdef CPU_SUPPORTED
	`or cpu_ce or tdo_cpu`
	`endif
	`)`
`begin`	`begin`
`if (shift_crc) // shifting crc`	`if (shift_crc) // shifting crc`
`tdo_tmp = crc_out;`	`tdo_tmp = crc_out;`
	`ifdef WISHBONE_SUPPORTED
`else if (wishbone_ce) // shifting data from wb`	`else if (wishbone_ce) // shifting data from wb`
`tdo_tmp = tdo_wb;`	`tdo_tmp = tdo_wb;`
	`endif
	`ifdef CPU_SUPPORTED
`else if (cpu_ce) // shifting data from cpu`	`else if (cpu_ce) // shifting data from cpu`
`tdo_tmp = tdo_cpu;`	`tdo_tmp = tdo_cpu;`
	`endif
`else`	`else`
`tdo_tmp = tdo_chain_select;`	`tdo_tmp = tdo_chain_select;`
`end`	`end`


Line 536...	Line 577...


`// Signals for WISHBONE module`	`// Signals for WISHBONE module`


`always @ (posedge tck_i or posedge wb_rst_i)`	`always @ (posedge tck_i or posedge rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (rst_i)`
`begin`	`begin`
	`ifdef WISHBONE_SUPPORTED
`wishbone_ce <= #1 1'b0;`	`wishbone_ce <= #1 1'b0;`
	`endif
	`ifdef CPU_SUPPORTED
`cpu_ce <= #1 1'b0;`	`cpu_ce <= #1 1'b0;`
	`endif
`end`	`end`
`else if(selecting_command & (~tdi_i))`	`else if(selecting_command & (~tdi_i))`
`begin`	`begin`
	`ifdef WISHBONE_SUPPORTED
`if (wishbone_scan_chain) // wishbone CE`	`if (wishbone_scan_chain) // wishbone CE`
`wishbone_ce <= #1 1'b1;`	`wishbone_ce <= #1 1'b1;`
	`endif
	`ifdef CPU_SUPPORTED
`if (cpu_debug_scan_chain) // CPU CE`	`if (cpu_debug_scan_chain) // CPU CE`
`cpu_ce <= #1 1'b1;`	`cpu_ce <= #1 1'b1;`
	`endif
`end`	`end`
`else if (update_dr_i) // igor !!! This needs to be changed?`	`else if (update_dr_i) // igor !!! This needs to be changed?`
`begin`	`begin`
	`ifdef WISHBONE_SUPPORTED
`wishbone_ce <= #1 1'b0;`	`wishbone_ce <= #1 1'b0;`
	`endif
	`ifdef CPU_SUPPORTED
`cpu_ce <= #1 1'b0;`	`cpu_ce <= #1 1'b0;`
	`endif
`end`	`end`
`end`	`end`


	`ifdef WISHBONE_SUPPORTED
`assign tdi_wb = wishbone_ce & tdi_i;`	`assign tdi_wb = wishbone_ce & tdi_i;`
	`endif

	`ifdef CPU_SUPPORTED
`assign tdi_cpu = cpu_ce & tdi_i;`	`assign tdi_cpu = cpu_ce & tdi_i;`
	`endif


	`ifdef WISHBONE_SUPPORTED
`// Connecting wishbone module`	`// Connecting wishbone module`
`dbg_wb i_dbg_wb (`	`dbg_wb i_dbg_wb (`
`// JTAG signals`	`// JTAG signals`
`.tck_i (tck_i),`	`.tck_i (tck_i),`
`.tdi_i (tdi_wb),`	`.tdi_i (tdi_wb),`
Line 578...	Line 637...

`.wishbone_ce_i (wishbone_ce),`	`.wishbone_ce_i (wishbone_ce),`
`.crc_match_i (crc_match),`	`.crc_match_i (crc_match),`
`.crc_en_o (crc_en_wb),`	`.crc_en_o (crc_en_wb),`
`.shift_crc_o (shift_crc_wb),`	`.shift_crc_o (shift_crc_wb),`
`.rst_i (wb_rst_i),`	`.rst_i (rst_i),`

`// WISHBONE common signals`	`// WISHBONE common signals`
`.wb_clk_i (wb_clk_i),`	`.wb_clk_i (wb_clk_i),`

`// WISHBONE master interface`	`// WISHBONE master interface`
Line 597...	Line 656...
`.wb_cab_o (wb_cab_o),`	`.wb_cab_o (wb_cab_o),`
`.wb_err_i (wb_err_i),`	`.wb_err_i (wb_err_i),`
`.wb_cti_o (wb_cti_o),`	`.wb_cti_o (wb_cti_o),`
`.wb_bte_o (wb_bte_o)`	`.wb_bte_o (wb_bte_o)`
`);`	`);`
	`endif


	`ifdef CPU_SUPPORTED
`// Connecting cpu module`	`// Connecting cpu module`
`dbg_cpu i_dbg_cpu (`	`dbg_cpu i_dbg_cpu (`
`// JTAG signals`	`// JTAG signals`
`.tck_i (tck_i),`	`.tck_i (tck_i),`
`.tdi_i (tdi_cpu),`	`.tdi_i (tdi_cpu),`
Line 615...	Line 676...

`.cpu_ce_i (cpu_ce),`	`.cpu_ce_i (cpu_ce),`
`.crc_match_i (crc_match),`	`.crc_match_i (crc_match),`
`.crc_en_o (crc_en_cpu),`	`.crc_en_o (crc_en_cpu),`
`.shift_crc_o (shift_crc_cpu),`	`.shift_crc_o (shift_crc_cpu),`
`.rst_i (wb_rst_i),`	`.rst_i (rst_i),`

`// CPU signals`	`// CPU signals`
`.cpu_clk_i (cpu_clk_i),`	`.cpu_clk_i (cpu_clk_i),`
`.cpu_addr_o (cpu_addr_o),`	`.cpu_addr_o (cpu_addr_o),`
`.cpu_data_i (cpu_data_i),`	`.cpu_data_i (cpu_data_i),`
Line 630...	Line 691...
`.cpu_stb_o (cpu_stb_o),`	`.cpu_stb_o (cpu_stb_o),`
`.cpu_sel_o (cpu_sel_o),`	`.cpu_sel_o (cpu_sel_o),`
`.cpu_we_o (cpu_we_o),`	`.cpu_we_o (cpu_we_o),`
`.cpu_ack_i (cpu_ack_i),`	`.cpu_ack_i (cpu_ack_i),`
`.cpu_rst_o (cpu_rst_o)`	`.cpu_rst_o (cpu_rst_o)`


`);`	`);`
	`endif // CPU_SUPPORTED



`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 123 and 128