| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.42 2004/01/30 10:24:31 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
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// turned on.
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//
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// Revision 1.41 2004/01/25 14:04:18 mohor
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// Revision 1.41 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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// All flipflops are reset.
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//
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//
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// Revision 1.40 2004/01/20 14:23:47 mohor
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// Revision 1.40 2004/01/20 14:23:47 mohor
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// Define name changed.
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// Define name changed.
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| Line 275... |
Line 279... |
output wb_cab_o;
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output wb_cab_o;
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input wb_err_i;
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input wb_err_i;
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output [2:0] wb_cti_o;
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output [2:0] wb_cti_o;
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output [1:0] wb_bte_o;
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output [1:0] wb_bte_o;
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reg wishbone_scan_chain;
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reg wishbone_module;
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reg wishbone_ce;
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reg wishbone_ce;
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wire tdi_wb;
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wire tdi_wb;
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wire tdo_wb;
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wire tdo_wb;
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wire crc_en_wb;
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wire crc_en_wb;
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wire shift_crc_wb;
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wire shift_crc_wb;
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| Line 301... |
Line 305... |
output [`CPU_NUM -1:0] cpu_sel_o;
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output [`CPU_NUM -1:0] cpu_sel_o;
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output cpu_we_o;
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output cpu_we_o;
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input cpu_ack_i;
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input cpu_ack_i;
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output cpu_rst_o;
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output cpu_rst_o;
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reg cpu_debug_scan_chain;
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reg cpu_debug_module;
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reg cpu_ce;
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reg cpu_ce;
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wire tdi_cpu;
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wire tdi_cpu;
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wire tdo_cpu;
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wire tdo_cpu;
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wire crc_en_cpu;
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wire crc_en_cpu;
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wire shift_crc_cpu;
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wire shift_crc_cpu;
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| Line 315... |
Line 319... |
`endif
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`endif
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reg [`DATA_CNT -1:0] data_cnt;
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reg [`DATA_CNT -1:0] data_cnt;
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reg [`CRC_CNT -1:0] crc_cnt;
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reg [`CRC_CNT -1:0] crc_cnt;
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reg [`STATUS_CNT -1:0] status_cnt;
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reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
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reg [`CHAIN_DATA_LEN -1:0] chain_dr;
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reg [`MODULE_DATA_LEN -1:0] module_dr;
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reg [`CHAIN_ID_LENGTH -1:0] chain;
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reg [`MODULE_ID_LENGTH -1:0] module_id;
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wire chain_latch_en;
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wire module_latch_en;
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wire data_cnt_end;
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wire data_cnt_end;
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wire crc_cnt_end;
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wire crc_cnt_end;
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wire status_cnt_end;
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wire status_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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reg chain_select;
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reg module_select;
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reg chain_select_error;
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reg module_select_error;
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wire crc_out;
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wire crc_out;
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wire crc_match;
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wire crc_match;
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wire data_shift_en;
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wire data_shift_en;
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wire selecting_command;
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wire selecting_command;
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| Line 351... |
Line 355... |
else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= #1 {`DATA_CNT{1'b0}};
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data_cnt <= #1 {`DATA_CNT{1'b0}};
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end
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end
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assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
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assign data_cnt_end = data_cnt == `MODULE_DATA_LEN;
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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crc_cnt <= #1 {`CRC_CNT{1'b0}};
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crc_cnt <= #1 {`CRC_CNT{1'b0}};
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
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crc_cnt <= #1 crc_cnt + 1'b1;
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crc_cnt <= #1 crc_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= #1 {`CRC_CNT{1'b0}};
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crc_cnt <= #1 {`CRC_CNT{1'b0}};
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end
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end
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assign crc_cnt_end = crc_cnt == `CRC_LEN;
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assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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| Line 381... |
Line 385... |
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// status counter
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// status counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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status_cnt <= #1 {`STATUS_CNT{1'b0}};
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status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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status_cnt <= #1 status_cnt + 1'b1;
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status_cnt <= #1 status_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt <= #1 {`STATUS_CNT{1'b0}};
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status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
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end
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end
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assign status_cnt_end = status_cnt == `STATUS_LEN;
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assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
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assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
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assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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chain_select <= #1 1'b0;
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module_select <= #1 1'b0;
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else if(selecting_command & tdi_i) // Chain select
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else if(selecting_command & tdi_i) // Chain select
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chain_select <= #1 1'b1;
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module_select <= #1 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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chain_select <= #1 1'b0;
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module_select <= #1 1'b0;
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end
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end
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always @ (chain)
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always @ (module_id)
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begin
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begin
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`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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cpu_debug_scan_chain <= #1 1'b0;
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cpu_debug_module <= #1 1'b0;
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`endif
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`endif
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`ifdef WISHBONE_SUPPORTED
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`ifdef WISHBONE_SUPPORTED
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wishbone_scan_chain <= #1 1'b0;
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wishbone_module <= #1 1'b0;
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`endif
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`endif
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chain_select_error <= #1 1'b0;
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module_select_error <= #1 1'b0;
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case (chain) /* synthesis parallel_case */
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case (module_id) /* synthesis parallel_case */
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`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1;
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`CPU_DEBUG_MODULE : cpu_debug_module <= #1 1'b1;
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`endif
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`endif
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`ifdef WISHBONE_SUPPORTED
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`ifdef WISHBONE_SUPPORTED
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`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1;
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`WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
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`endif
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`endif
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default : chain_select_error <= #1 1'b1;
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default : module_select_error <= #1 1'b1;
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endcase
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endcase
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end
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end
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assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q);
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assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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chain <= `CHAIN_ID_LENGTH'b111;
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module_id <= {`MODULE_ID_LENGTH{1'b1}};
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else if(chain_latch_en & crc_match)
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else if(module_latch_en & crc_match)
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chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
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module_id <= #1 module_dr[`MODULE_DATA_LEN -2:0];
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end
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end
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assign data_shift_en = shift_dr_i & (~data_cnt_end);
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assign data_shift_en = shift_dr_i & (~data_cnt_end);
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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chain_dr <= #1 `CHAIN_DATA_LEN'h0;
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module_dr <= #1 `MODULE_DATA_LEN'h0;
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else if (data_shift_en)
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else if (data_shift_en)
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chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]};
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module_dr[`MODULE_DATA_LEN -1:0] <= #1 {module_dr[`MODULE_DATA_LEN -2:0], tdi_i};
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end
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end
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// Calculating crc for input data
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// Calculating crc for input data
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dbg_crc32_d1 i_dbg_crc32_d1_in
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dbg_crc32_d1 i_dbg_crc32_d1_in
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| Line 465... |
Line 469... |
.clk (tck_i),
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.clk (tck_i),
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.crc_match (crc_match)
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.crc_match (crc_match)
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);
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);
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reg tdo_chain_select;
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reg tdo_module_select;
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wire crc_en;
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wire crc_en;
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wire crc_en_dbg;
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wire crc_en_dbg;
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reg crc_started;
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reg crc_started;
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assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
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assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
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| Line 503... |
Line 507... |
.clk (tck_i),
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.clk (tck_i),
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.crc_match ()
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.crc_match ()
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);
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);
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// Following status is shifted out:
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// Following status is shifted out:
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// 1. bit: 1 if crc is OK, else 0
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// 1. bit: 0 if crc is OK, else 1
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// 2. bit: 1 if command is "chain select", else 0
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// 2. bit: 0 if command is "module_id select", else 1
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// 3. bit: 1 if non-existing chain is selected else 0
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// 3. bit: 0 if existing module_id is selected else, 1 if non-existing module_id is selected
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// 4. bit: always 1
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// 4. bit: 0 (always)
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reg [799:0] current_on_tdo;
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always @ (status_cnt or chain_select or crc_match or chain_select_error or crc_out)
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always @ (status_cnt or module_select or crc_match or module_select_error or crc_out)
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begin
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begin
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case (status_cnt) /* synthesis full_case parallel_case */
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case (status_cnt) /* synthesis full_case parallel_case */
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`STATUS_CNT'd0 : begin
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`DBG_TOP_STATUS_CNT_WIDTH'd0 : begin
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tdo_chain_select = crc_match;
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tdo_module_select = ~crc_match;
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current_on_tdo = "crc_match";
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end
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end
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`DBG_TOP_STATUS_CNT_WIDTH'd1 : begin
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`STATUS_CNT'd1 : begin
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tdo_module_select = ~module_select;
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tdo_chain_select = chain_select;
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end
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current_on_tdo = "chain_select";
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`DBG_TOP_STATUS_CNT_WIDTH'd2 : begin
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end
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tdo_module_select = module_select_error;
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`STATUS_CNT'd2 : begin
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end
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tdo_chain_select = chain_select_error;
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`DBG_TOP_STATUS_CNT_WIDTH'd3 : begin
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current_on_tdo = "chain_select_error";
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tdo_module_select = 1'b0;
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end
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end
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`STATUS_CNT'd3 : begin
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`DBG_TOP_STATUS_CNT_WIDTH'd4 : begin
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tdo_chain_select = 1'b1;
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tdo_module_select = crc_out;
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current_on_tdo = "one 1";
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end
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`STATUS_CNT'd4 : begin
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tdo_chain_select = crc_out;
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// tdo_chain_select = 1'hz;
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current_on_tdo = "crc_out";
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end
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end
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endcase
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endcase
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end
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end
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assign shift_crc = shift_crc_wb | shift_crc_cpu;
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assign shift_crc = shift_crc_wb | shift_crc_cpu;
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always @ (shift_crc or crc_out or tdo_chain_select
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always @ (shift_crc or crc_out or tdo_module_select
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`ifdef WISHBONE_SUPPORTED
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`ifdef WISHBONE_SUPPORTED
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or wishbone_ce or tdo_wb
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or wishbone_ce or tdo_wb
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`endif
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`endif
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`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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or cpu_ce or tdo_cpu
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or cpu_ce or tdo_cpu
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| Line 562... |
Line 559... |
`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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else if (cpu_ce) // shifting data from cpu
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else if (cpu_ce) // shifting data from cpu
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tdo_tmp = tdo_cpu;
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tdo_tmp = tdo_cpu;
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`endif
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`endif
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else
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else
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tdo_tmp = tdo_chain_select;
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tdo_tmp = tdo_module_select;
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end
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end
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always @ (negedge tck_i)
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always @ (negedge tck_i)
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begin
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begin
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| Line 591... |
Line 588... |
`endif
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`endif
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end
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end
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else if(selecting_command & (~tdi_i))
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else if(selecting_command & (~tdi_i))
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begin
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begin
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`ifdef WISHBONE_SUPPORTED
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`ifdef WISHBONE_SUPPORTED
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if (wishbone_scan_chain) // wishbone CE
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if (wishbone_module) // wishbone CE
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wishbone_ce <= #1 1'b1;
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wishbone_ce <= #1 1'b1;
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`endif
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`endif
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`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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if (cpu_debug_scan_chain) // CPU CE
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if (cpu_debug_module) // CPU CE
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cpu_ce <= #1 1'b1;
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cpu_ce <= #1 1'b1;
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`endif
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`endif
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end
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end
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else if (update_dr_i) // igor !!! This needs to be changed?
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else if (update_dr_i)
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begin
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begin
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`ifdef WISHBONE_SUPPORTED
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`ifdef WISHBONE_SUPPORTED
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wishbone_ce <= #1 1'b0;
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wishbone_ce <= #1 1'b0;
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`endif
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`endif
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`ifdef CPU_SUPPORTED
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`ifdef CPU_SUPPORTED
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