| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// dbg_top.v ////
|
//// dbg_top.v ////
|
//// ////
|
//// ////
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//// ////
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//// ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// This file is part of the SoC Debug Interface. ////
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
|
//// ////
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| Line 13... |
Line 13... |
//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 - 2003 Authors ////
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//// Copyright (C) 2000 - 2004 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.43 2004/03/22 16:35:46 igorm
|
|
// Temp version before changing dbg interface.
|
|
//
|
// Revision 1.42 2004/01/30 10:24:31 mohor
|
// Revision 1.42 2004/01/30 10:24:31 mohor
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
// turned on.
|
// turned on.
|
//
|
//
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// Revision 1.41 2004/01/25 14:04:18 mohor
|
// Revision 1.41 2004/01/25 14:04:18 mohor
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| Line 211... |
Line 214... |
|
|
// Instructions
|
// Instructions
|
debug_select_i
|
debug_select_i
|
|
|
|
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// WISHBONE common signals
|
// WISHBONE common signals
|
,
|
,
|
wb_clk_i,
|
wb_clk_i,
|
|
|
// WISHBONE master interface
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// WISHBONE master interface
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| Line 231... |
Line 234... |
wb_err_i,
|
wb_err_i,
|
wb_cti_o,
|
wb_cti_o,
|
wb_bte_o
|
wb_bte_o
|
`endif
|
`endif
|
|
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
// CPU signals
|
// CPU signals
|
,
|
,
|
cpu_clk_i,
|
cpu_clk_i,
|
cpu_addr_o,
|
cpu_addr_o,
|
cpu_data_i,
|
cpu_data_i,
|
cpu_data_o,
|
cpu_data_o,
|
cpu_bp_i,
|
cpu_bp_i,
|
cpu_stall_o,
|
cpu_stall_o,
|
cpu_stall_all_o,
|
|
cpu_stb_o,
|
cpu_stb_o,
|
cpu_sel_o,
|
|
cpu_we_o,
|
cpu_we_o,
|
cpu_ack_i,
|
cpu_ack_i,
|
cpu_rst_o
|
cpu_rst_o
|
`endif
|
`endif
|
);
|
);
|
| Line 264... |
Line 265... |
input update_dr_i;
|
input update_dr_i;
|
|
|
// Instructions
|
// Instructions
|
input debug_select_i;
|
input debug_select_i;
|
|
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
input wb_clk_i;
|
input wb_clk_i;
|
output [31:0] wb_adr_o;
|
output [31:0] wb_adr_o;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_cyc_o;
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| Line 290... |
Line 291... |
`else
|
`else
|
wire crc_en_wb = 1'b0;
|
wire crc_en_wb = 1'b0;
|
wire shift_crc_wb = 1'b0;
|
wire shift_crc_wb = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
// CPU signals
|
// CPU signals
|
input cpu_clk_i;
|
input cpu_clk_i;
|
output [31:0] cpu_addr_o;
|
output [31:0] cpu_addr_o;
|
input [31:0] cpu_data_i;
|
input [31:0] cpu_data_i;
|
output [31:0] cpu_data_o;
|
output [31:0] cpu_data_o;
|
input cpu_bp_i;
|
input cpu_bp_i;
|
output cpu_stall_o;
|
output cpu_stall_o;
|
output cpu_stall_all_o;
|
|
output cpu_stb_o;
|
output cpu_stb_o;
|
output [`CPU_NUM -1:0] cpu_sel_o;
|
|
output cpu_we_o;
|
output cpu_we_o;
|
input cpu_ack_i;
|
input cpu_ack_i;
|
output cpu_rst_o;
|
output cpu_rst_o;
|
|
|
reg cpu_debug_module;
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reg cpu_debug_module;
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| Line 317... |
Line 316... |
wire crc_en_cpu = 1'b0;
|
wire crc_en_cpu = 1'b0;
|
wire shift_crc_cpu = 1'b0;
|
wire shift_crc_cpu = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
reg [`DATA_CNT -1:0] data_cnt;
|
reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
|
reg [`CRC_CNT -1:0] crc_cnt;
|
reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
|
reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
|
reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
|
reg [`MODULE_DATA_LEN -1:0] module_dr;
|
reg [`DBG_TOP_MODULE_DATA_LEN -1:0] module_dr;
|
reg [`MODULE_ID_LENGTH -1:0] module_id;
|
reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id;
|
|
|
wire module_latch_en;
|
wire module_latch_en;
|
wire data_cnt_end;
|
wire data_cnt_end;
|
wire crc_cnt_end;
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wire crc_cnt_end;
|
wire status_cnt_end;
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wire status_cnt_end;
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| Line 347... |
Line 346... |
|
|
// data counter
|
// data counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
data_cnt <= #1 {`DATA_CNT{1'b0}};
|
data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}};
|
else if(shift_dr_i & (~data_cnt_end))
|
else if(shift_dr_i & (~data_cnt_end))
|
data_cnt <= #1 data_cnt + 1'b1;
|
data_cnt <= #1 data_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
data_cnt <= #1 {`DATA_CNT{1'b0}};
|
data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}};
|
end
|
end
|
|
|
|
|
assign data_cnt_end = data_cnt == `MODULE_DATA_LEN;
|
assign data_cnt_end = data_cnt == `DBG_TOP_MODULE_DATA_LEN;
|
|
|
|
|
// crc counter
|
// crc counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
crc_cnt <= #1 {`CRC_CNT{1'b0}};
|
crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}};
|
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
|
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
crc_cnt <= #1 {`CRC_CNT{1'b0}};
|
crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}};
|
end
|
end
|
|
|
assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
|
assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
|
|
|
|
|
| Line 395... |
Line 394... |
end
|
end
|
|
|
assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
|
assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
|
|
|
|
|
assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
|
assign selecting_command = shift_dr_i & (data_cnt == `DBG_TOP_DATA_CNT'h0) & debug_select_i;
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
| Line 411... |
Line 410... |
end
|
end
|
|
|
|
|
always @ (module_id)
|
always @ (module_id)
|
begin
|
begin
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
cpu_debug_module <= #1 1'b0;
|
cpu_debug_module <= #1 1'b0;
|
`endif
|
`endif
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_module <= #1 1'b0;
|
wishbone_module <= #1 1'b0;
|
`endif
|
`endif
|
module_select_error <= #1 1'b0;
|
module_select_error <= #1 1'b0;
|
|
|
case (module_id) /* synthesis parallel_case */
|
case (module_id) /* synthesis parallel_case */
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
`CPU_DEBUG_MODULE : cpu_debug_module <= #1 1'b1;
|
`DBG_TOP_CPU_DEBUG_MODULE : cpu_debug_module <= #1 1'b1;
|
`endif
|
`endif
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
|
`DBG_TOP_WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
|
`endif
|
`endif
|
default : module_select_error <= #1 1'b1;
|
default : module_select_error <= #1 1'b1;
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 437... |
Line 436... |
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
module_id <= {`MODULE_ID_LENGTH{1'b1}};
|
module_id <= {`DBG_TOP_MODULE_ID_LENGTH{1'b1}};
|
else if(module_latch_en & crc_match)
|
else if(module_latch_en & crc_match)
|
module_id <= #1 module_dr[`MODULE_DATA_LEN -2:0];
|
module_id <= #1 module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0];
|
end
|
end
|
|
|
|
|
assign data_shift_en = shift_dr_i & (~data_cnt_end);
|
assign data_shift_en = shift_dr_i & (~data_cnt_end);
|
|
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
module_dr <= #1 `MODULE_DATA_LEN'h0;
|
module_dr <= #1 `DBG_TOP_MODULE_DATA_LEN'h0;
|
else if (data_shift_en)
|
else if (data_shift_en)
|
module_dr[`MODULE_DATA_LEN -1:0] <= #1 {module_dr[`MODULE_DATA_LEN -2:0], tdi_i};
|
module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= #1 {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
|
end
|
end
|
|
|
|
|
// Calculating crc for input data
|
// Calculating crc for input data
|
dbg_crc32_d1 i_dbg_crc32_d1_in
|
dbg_crc32_d1 i_dbg_crc32_d1_in
|
| Line 508... |
Line 507... |
.crc_match ()
|
.crc_match ()
|
);
|
);
|
|
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 0 if crc is OK, else 1
|
// 1. bit: 0 if crc is OK, else 1
|
// 2. bit: 0 if command is "module_id select", else 1
|
// 2. bit: 0 if existing module_id is selected, 1 if non-existing module_id is selected
|
// 3. bit: 0 if existing module_id is selected else, 1 if non-existing module_id is selected
|
// 3. bit: 0 (always)
|
// 4. bit: 0 (always)
|
// 4. bit: 0 (always)
|
|
|
|
|
always @ (status_cnt or module_select or crc_match or module_select_error or crc_out)
|
always @ (status_cnt or crc_match or module_select_error or crc_out)
|
begin
|
begin
|
case (status_cnt) /* synthesis full_case parallel_case */
|
case (status_cnt) /* synthesis full_case parallel_case */
|
`DBG_TOP_STATUS_CNT_WIDTH'd0 : begin
|
`DBG_TOP_STATUS_CNT_WIDTH'd0 : begin
|
tdo_module_select = ~crc_match;
|
tdo_module_select = ~crc_match;
|
end
|
end
|
`DBG_TOP_STATUS_CNT_WIDTH'd1 : begin
|
`DBG_TOP_STATUS_CNT_WIDTH'd1 : begin
|
tdo_module_select = ~module_select;
|
tdo_module_select = module_select_error;
|
end
|
end
|
`DBG_TOP_STATUS_CNT_WIDTH'd2 : begin
|
`DBG_TOP_STATUS_CNT_WIDTH'd2 : begin
|
tdo_module_select = module_select_error;
|
tdo_module_select = 1'b0;
|
end
|
end
|
`DBG_TOP_STATUS_CNT_WIDTH'd3 : begin
|
`DBG_TOP_STATUS_CNT_WIDTH'd3 : begin
|
tdo_module_select = 1'b0;
|
tdo_module_select = 1'b0;
|
end
|
end
|
`DBG_TOP_STATUS_CNT_WIDTH'd4 : begin
|
`DBG_TOP_STATUS_CNT_WIDTH'd4 : begin
|
| Line 540... |
Line 539... |
|
|
|
|
assign shift_crc = shift_crc_wb | shift_crc_cpu;
|
assign shift_crc = shift_crc_wb | shift_crc_cpu;
|
|
|
always @ (shift_crc or crc_out or tdo_module_select
|
always @ (shift_crc or crc_out or tdo_module_select
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
or wishbone_ce or tdo_wb
|
or wishbone_ce or tdo_wb
|
`endif
|
`endif
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
or cpu_ce or tdo_cpu
|
or cpu_ce or tdo_cpu
|
`endif
|
`endif
|
)
|
)
|
begin
|
begin
|
if (shift_crc) // shifting crc
|
if (shift_crc) // shifting crc
|
tdo_tmp = crc_out;
|
tdo_tmp = crc_out;
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
else if (wishbone_ce) // shifting data from wb
|
else if (wishbone_ce) // shifting data from wb
|
tdo_tmp = tdo_wb;
|
tdo_tmp = tdo_wb;
|
`endif
|
`endif
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
else if (cpu_ce) // shifting data from cpu
|
else if (cpu_ce) // shifting data from cpu
|
tdo_tmp = tdo_cpu;
|
tdo_tmp = tdo_cpu;
|
`endif
|
`endif
|
else
|
else
|
tdo_tmp = tdo_module_select;
|
tdo_tmp = tdo_module_select;
|
| Line 578... |
Line 577... |
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_ce <= #1 1'b0;
|
wishbone_ce <= #1 1'b0;
|
`endif
|
`endif
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
cpu_ce <= #1 1'b0;
|
cpu_ce <= #1 1'b0;
|
`endif
|
`endif
|
end
|
end
|
else if(selecting_command & (~tdi_i))
|
else if(selecting_command & (~tdi_i))
|
begin
|
begin
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
if (wishbone_module) // wishbone CE
|
if (wishbone_module) // wishbone CE
|
wishbone_ce <= #1 1'b1;
|
wishbone_ce <= #1 1'b1;
|
`endif
|
`endif
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
if (cpu_debug_module) // CPU CE
|
if (cpu_debug_module) // CPU CE
|
cpu_ce <= #1 1'b1;
|
cpu_ce <= #1 1'b1;
|
`endif
|
`endif
|
end
|
end
|
else if (update_dr_i)
|
else if (update_dr_i)
|
begin
|
begin
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_ce <= #1 1'b0;
|
wishbone_ce <= #1 1'b0;
|
`endif
|
`endif
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
cpu_ce <= #1 1'b0;
|
cpu_ce <= #1 1'b0;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
|
|
|
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
assign tdi_wb = wishbone_ce & tdi_i;
|
assign tdi_wb = wishbone_ce & tdi_i;
|
`endif
|
`endif
|
|
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
assign tdi_cpu = cpu_ce & tdi_i;
|
assign tdi_cpu = cpu_ce & tdi_i;
|
`endif
|
`endif
|
|
|
|
|
`ifdef WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// Connecting wishbone module
|
// Connecting wishbone module
|
dbg_wb i_dbg_wb (
|
dbg_wb i_dbg_wb (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.tdi_i (tdi_wb),
|
.tdi_i (tdi_wb),
|
| Line 656... |
Line 655... |
.wb_bte_o (wb_bte_o)
|
.wb_bte_o (wb_bte_o)
|
);
|
);
|
`endif
|
`endif
|
|
|
|
|
`ifdef CPU_SUPPORTED
|
`ifdef DBG_CPU_SUPPORTED
|
// Connecting cpu module
|
// Connecting cpu module
|
dbg_cpu i_dbg_cpu (
|
dbg_cpu i_dbg_cpu (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.tdi_i (tdi_cpu),
|
.tdi_i (tdi_cpu),
|
| Line 682... |
Line 681... |
.cpu_addr_o (cpu_addr_o),
|
.cpu_addr_o (cpu_addr_o),
|
.cpu_data_i (cpu_data_i),
|
.cpu_data_i (cpu_data_i),
|
.cpu_data_o (cpu_data_o),
|
.cpu_data_o (cpu_data_o),
|
.cpu_bp_i (cpu_bp_i),
|
.cpu_bp_i (cpu_bp_i),
|
.cpu_stall_o (cpu_stall_o),
|
.cpu_stall_o (cpu_stall_o),
|
.cpu_stall_all_o (cpu_stall_all_o),
|
|
.cpu_stb_o (cpu_stb_o),
|
.cpu_stb_o (cpu_stb_o),
|
.cpu_sel_o (cpu_sel_o),
|
|
.cpu_we_o (cpu_we_o),
|
.cpu_we_o (cpu_we_o),
|
.cpu_ack_i (cpu_ack_i),
|
.cpu_ack_i (cpu_ack_i),
|
.cpu_rst_o (cpu_rst_o)
|
.cpu_rst_o (cpu_rst_o)
|
);
|
);
|
`endif // CPU_SUPPORTED
|
`endif // DBG_CPU_SUPPORTED
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
|
