| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
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// CVS Revision History
|
//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.44 2004/03/28 20:27:02 igorm
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|
// New release of the debug interface (3rd. release).
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|
//
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// Revision 1.43 2004/03/22 16:35:46 igorm
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// Revision 1.43 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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// Temp version before changing dbg interface.
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//
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//
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// Revision 1.42 2004/01/30 10:24:31 mohor
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// Revision 1.42 2004/01/30 10:24:31 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
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| Line 234... |
Line 237... |
wb_err_i,
|
wb_err_i,
|
wb_cti_o,
|
wb_cti_o,
|
wb_bte_o
|
wb_bte_o
|
`endif
|
`endif
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|
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
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|
// CPU signals
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|
,
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|
cpu0_clk_i,
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|
cpu0_addr_o,
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|
cpu0_data_i,
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|
cpu0_data_o,
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|
cpu0_bp_i,
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|
cpu0_stall_o,
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|
cpu0_stb_o,
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|
cpu0_we_o,
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cpu0_ack_i,
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|
cpu0_rst_o
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|
`endif
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|
|
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`ifdef DBG_CPU1_SUPPORTED
|
// CPU signals
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// CPU signals
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,
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,
|
cpu_clk_i,
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cpu1_clk_i,
|
cpu_addr_o,
|
cpu1_addr_o,
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cpu_data_i,
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cpu1_data_i,
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cpu_data_o,
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cpu1_data_o,
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cpu_bp_i,
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cpu1_bp_i,
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cpu_stall_o,
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cpu1_stall_o,
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cpu_stb_o,
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cpu1_stb_o,
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cpu_we_o,
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cpu1_we_o,
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cpu_ack_i,
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cpu1_ack_i,
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cpu_rst_o
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cpu1_rst_o
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`endif
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`endif
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|
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);
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);
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|
|
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// JTAG signals
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// JTAG signals
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input tck_i;
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input tck_i;
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| Line 291... |
Line 310... |
`else
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`else
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wire crc_en_wb = 1'b0;
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wire crc_en_wb = 1'b0;
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wire shift_crc_wb = 1'b0;
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wire shift_crc_wb = 1'b0;
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`endif
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`endif
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|
|
`ifdef DBG_CPU_SUPPORTED
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`ifdef DBG_CPU0_SUPPORTED
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// CPU signals
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// CPU signals
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input cpu_clk_i;
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input cpu0_clk_i;
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output [31:0] cpu_addr_o;
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output [31:0] cpu0_addr_o;
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input [31:0] cpu_data_i;
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input [31:0] cpu0_data_i;
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output [31:0] cpu_data_o;
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output [31:0] cpu0_data_o;
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input cpu_bp_i;
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input cpu0_bp_i;
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output cpu_stall_o;
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output cpu0_stall_o;
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output cpu_stb_o;
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output cpu0_stb_o;
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output cpu_we_o;
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output cpu0_we_o;
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input cpu_ack_i;
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input cpu0_ack_i;
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output cpu_rst_o;
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output cpu0_rst_o;
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|
|
reg cpu_debug_module;
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reg cpu0_debug_module;
|
reg cpu_ce;
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reg cpu0_ce;
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wire tdi_cpu;
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wire cpu0_tdi;
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wire tdo_cpu;
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wire cpu0_tdo;
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wire crc_en_cpu;
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wire cpu0_crc_en;
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wire shift_crc_cpu;
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wire cpu0_shift_crc;
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`else
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|
wire cpu0_crc_en = 1'b0;
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|
wire cpu0_shift_crc = 1'b0;
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|
`endif
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|
|
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`ifdef DBG_CPU1_SUPPORTED
|
|
input cpu1_clk_i;
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|
output [31:0] cpu1_addr_o;
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input [31:0] cpu1_data_i;
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output [31:0] cpu1_data_o;
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input cpu1_bp_i;
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output cpu1_stall_o;
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output cpu1_stb_o;
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output cpu1_we_o;
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input cpu1_ack_i;
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output cpu1_rst_o;
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|
|
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reg cpu1_debug_module;
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reg cpu1_ce;
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wire cpu1_tdi;
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|
wire cpu1_tdo;
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wire cpu1_crc_en;
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wire cpu1_shift_crc;
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`else
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`else
|
wire crc_en_cpu = 1'b0;
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wire cpu1_crc_en = 1'b0;
|
wire shift_crc_cpu = 1'b0;
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wire cpu1_shift_crc = 1'b0;
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`endif
|
`endif
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|
|
|
|
reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
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reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
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reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
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reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
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| Line 410... |
Line 452... |
end
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end
|
|
|
|
|
always @ (module_id)
|
always @ (module_id)
|
begin
|
begin
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
cpu_debug_module <= #1 1'b0;
|
cpu0_debug_module <= #1 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
cpu1_debug_module <= #1 1'b0;
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`endif
|
`endif
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`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_module <= #1 1'b0;
|
wishbone_module <= #1 1'b0;
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`endif
|
`endif
|
module_select_error <= #1 1'b0;
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module_select_error <= #1 1'b0;
|
|
|
case (module_id) /* synthesis parallel_case */
|
case (module_id) /* synthesis parallel_case */
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`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
`DBG_TOP_CPU_DEBUG_MODULE : cpu_debug_module <= #1 1'b1;
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`DBG_TOP_CPU0_DEBUG_MODULE : cpu0_debug_module <= #1 1'b1;
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|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
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|
`DBG_TOP_CPU1_DEBUG_MODULE : cpu1_debug_module <= #1 1'b1;
|
`endif
|
`endif
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`DBG_TOP_WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
|
`DBG_TOP_WISHBONE_DEBUG_MODULE: wishbone_module <= #1 1'b1;
|
`endif
|
`endif
|
default : module_select_error <= #1 1'b1;
|
default : module_select_error <= #1 1'b1;
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| Line 473... |
Line 521... |
reg tdo_module_select;
|
reg tdo_module_select;
|
wire crc_en;
|
wire crc_en;
|
wire crc_en_dbg;
|
wire crc_en_dbg;
|
reg crc_started;
|
reg crc_started;
|
|
|
assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
|
assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
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|
|
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
|
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
|
|
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
| Line 536... |
Line 584... |
end
|
end
|
|
|
|
|
|
|
|
|
assign shift_crc = shift_crc_wb | shift_crc_cpu;
|
assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
|
|
|
always @ (shift_crc or crc_out or tdo_module_select
|
always @ (shift_crc or crc_out or tdo_module_select
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
or wishbone_ce or tdo_wb
|
or wishbone_ce or tdo_wb
|
`endif
|
`endif
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
or cpu_ce or tdo_cpu
|
or cpu0_ce or cpu0_tdo
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
or cpu1_ce or cpu1_tdo
|
`endif
|
`endif
|
)
|
)
|
begin
|
begin
|
if (shift_crc) // shifting crc
|
if (shift_crc) // shifting crc
|
tdo_tmp = crc_out;
|
tdo_tmp = crc_out;
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
else if (wishbone_ce) // shifting data from wb
|
else if (wishbone_ce) // shifting data from wb
|
tdo_tmp = tdo_wb;
|
tdo_tmp = tdo_wb;
|
`endif
|
`endif
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
else if (cpu_ce) // shifting data from cpu
|
else if (cpu0_ce) // shifting data from cpu
|
tdo_tmp = tdo_cpu;
|
tdo_tmp = cpu0_tdo;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
else if (cpu1_ce) // shifting data from cpu
|
|
tdo_tmp = cpu1_tdo;
|
`endif
|
`endif
|
else
|
else
|
tdo_tmp = tdo_module_select;
|
tdo_tmp = tdo_module_select;
|
end
|
end
|
|
|
| Line 580... |
Line 635... |
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_ce <= #1 1'b0;
|
wishbone_ce <= #1 1'b0;
|
`endif
|
`endif
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
cpu_ce <= #1 1'b0;
|
cpu0_ce <= #1 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
cpu1_ce <= #1 1'b0;
|
`endif
|
`endif
|
end
|
end
|
else if(selecting_command & (~tdi_i))
|
else if(selecting_command & (~tdi_i))
|
begin
|
begin
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
if (wishbone_module) // wishbone CE
|
if (wishbone_module) // wishbone CE
|
wishbone_ce <= #1 1'b1;
|
wishbone_ce <= #1 1'b1;
|
`endif
|
`endif
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
if (cpu_debug_module) // CPU CE
|
if (cpu0_debug_module) // CPU CE
|
cpu_ce <= #1 1'b1;
|
cpu0_ce <= #1 1'b1;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
if (cpu1_debug_module) // CPU CE
|
|
cpu1_ce <= #1 1'b1;
|
`endif
|
`endif
|
end
|
end
|
else if (update_dr_i)
|
else if (update_dr_i)
|
begin
|
begin
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
wishbone_ce <= #1 1'b0;
|
wishbone_ce <= #1 1'b0;
|
`endif
|
`endif
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
cpu_ce <= #1 1'b0;
|
cpu0_ce <= #1 1'b0;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
cpu1_ce <= #1 1'b0;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
assign tdi_wb = wishbone_ce & tdi_i;
|
assign tdi_wb = wishbone_ce & tdi_i;
|
`endif
|
`endif
|
|
|
`ifdef DBG_CPU_SUPPORTED
|
`ifdef DBG_CPU0_SUPPORTED
|
assign tdi_cpu = cpu_ce & tdi_i;
|
assign cpu0_tdi = cpu0_ce & tdi_i;
|
|
`endif
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
assign cpu1_tdi = cpu1_ce & tdi_i;
|
`endif
|
`endif
|
|
|
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
`ifdef DBG_WISHBONE_SUPPORTED
|
// Connecting wishbone module
|
// Connecting wishbone module
|
| Line 655... |
Line 723... |
.wb_bte_o (wb_bte_o)
|
.wb_bte_o (wb_bte_o)
|
);
|
);
|
`endif
|
`endif
|
|
|
|
|
`ifdef DBG_CPU_SUPPORTED
|
|
// Connecting cpu module
|
`ifdef DBG_CPU0_SUPPORTED
|
dbg_cpu i_dbg_cpu (
|
dbg_cpu i_dbg_cpu_or1k (
|
// JTAG signals
|
// JTAG signals
|
.tck_i (tck_i),
|
.tck_i (tck_i),
|
.tdi_i (tdi_cpu),
|
.tdi_i (cpu0_tdi),
|
.tdo_o (tdo_cpu),
|
.tdo_o (cpu0_tdo),
|
|
|
// TAP states
|
// TAP states
|
.shift_dr_i (shift_dr_i),
|
.shift_dr_i (shift_dr_i),
|
.pause_dr_i (pause_dr_i),
|
.pause_dr_i (pause_dr_i),
|
.update_dr_i (update_dr_i),
|
.update_dr_i (update_dr_i),
|
|
|
.cpu_ce_i (cpu_ce),
|
.cpu_ce_i (cpu0_ce),
|
.crc_match_i (crc_match),
|
.crc_match_i (crc_match),
|
.crc_en_o (crc_en_cpu),
|
.crc_en_o (cpu0_crc_en),
|
.shift_crc_o (shift_crc_cpu),
|
.shift_crc_o (cpu0_shift_crc),
|
.rst_i (rst_i),
|
.rst_i (rst_i),
|
|
|
// CPU signals
|
// CPU signals
|
.cpu_clk_i (cpu_clk_i),
|
.cpu_clk_i (cpu0_clk_i),
|
.cpu_addr_o (cpu_addr_o),
|
.cpu_addr_o (cpu0_addr_o),
|
.cpu_data_i (cpu_data_i),
|
.cpu_data_i (cpu0_data_i),
|
.cpu_data_o (cpu_data_o),
|
.cpu_data_o (cpu0_data_o),
|
.cpu_bp_i (cpu_bp_i),
|
.cpu_bp_i (cpu0_bp_i),
|
.cpu_stall_o (cpu_stall_o),
|
.cpu_stall_o (cpu0_stall_o),
|
.cpu_stb_o (cpu_stb_o),
|
.cpu_stb_o (cpu0_stb_o),
|
.cpu_we_o (cpu_we_o),
|
.cpu_we_o (cpu0_we_o),
|
.cpu_ack_i (cpu_ack_i),
|
.cpu_ack_i (cpu0_ack_i),
|
.cpu_rst_o (cpu_rst_o)
|
.cpu_rst_o (cpu0_rst_o)
|
);
|
);
|
`endif // DBG_CPU_SUPPORTED
|
|
|
|
|
`endif // DBG_CPU0_SUPPORTED
|
|
|
|
|
|
|
|
`ifdef DBG_CPU1_SUPPORTED
|
|
// Connecting cpu module
|
|
dbg_cpu i_dbg_cpu_8051 (
|
|
// JTAG signals
|
|
.tck_i (tck_i),
|
|
.tdi_i (cpu1_tdi),
|
|
.tdo_o (cpu1_tdo),
|
|
|
|
// TAP states
|
|
.shift_dr_i (shift_dr_i),
|
|
.pause_dr_i (pause_dr_i),
|
|
.update_dr_i (update_dr_i),
|
|
|
|
.cpu_ce_i (cpu1_ce),
|
|
.crc_match_i (crc_match),
|
|
.crc_en_o (cpu1_crc_en),
|
|
.shift_crc_o (cpu1_shift_crc),
|
|
.rst_i (rst_i),
|
|
|
|
// CPU signals
|
|
.cpu_clk_i (cpu1_clk_i),
|
|
.cpu_addr_o (cpu1_addr_o),
|
|
.cpu_data_i (cpu1_data_i),
|
|
.cpu_data_o (cpu1_data_o),
|
|
.cpu_bp_i (cpu1_bp_i),
|
|
.cpu_stall_o (cpu1_stall_o),
|
|
.cpu_stb_o (cpu1_stb_o),
|
|
.cpu_we_o (cpu1_we_o),
|
|
.cpu_ack_i (cpu1_ack_i),
|
|
.cpu_rst_o (cpu1_rst_o)
|
|
);
|
|
`endif
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
