Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.13 2001/11/27 13:37:43 mohor
|
|
// CRC is returned when chain selection data is transmitted.
|
|
//
|
// Revision 1.12 2001/11/26 10:47:09 mohor
|
// Revision 1.12 2001/11/26 10:47:09 mohor
|
// Crc generation is different for read or write commands. Small synthesys fixes.
|
// Crc generation is different for read or write commands. Small synthesys fixes.
|
//
|
//
|
// Revision 1.11 2001/11/14 10:10:41 mohor
|
// Revision 1.11 2001/11/14 10:10:41 mohor
|
// Wishbone data latched on wb_clk_i instead of risc_clk.
|
// Wishbone data latched on wb_clk_i instead of risc_clk.
|
Line 634... |
Line 637... |
else
|
else
|
if(ShiftDR)
|
if(ShiftDR)
|
JTAG_DR_IN[BitCounter]<=#Tp TDI;
|
JTAG_DR_IN[BitCounter]<=#Tp TDI;
|
end
|
end
|
|
|
wire [72:0] RISC_Data;
|
wire [73:0] RISC_Data;
|
wire [45:0] Register_Data;
|
wire [46:0] Register_Data;
|
wire [72:0] WISHBONE_Data;
|
wire [73:0] WISHBONE_Data;
|
wire [12:0] chain_sel_data;
|
wire [12:0] chain_sel_data;
|
wire wb_Access_wbClk;
|
wire wb_Access_wbClk;
|
|
|
// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
|
// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
|
// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
|
// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
|