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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Revision 1.25 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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// Signal names changed to lower case.
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//
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//
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Revision 1.24 2002/04/17 13:17:01 mohor
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// Intentional error removed.
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// Intentional error removed.
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Line 249... |
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
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reg RISCAccess_q2; // Delayed signals used for accessing the RISC
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBInProgress; // WISHBONE access is in progress
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reg [7:0] WBAccessCounter; // Counting access cycles. WBInProgress is cleared to 0 after counter exceeds 0xff
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wire WBAccessCounterExceed; // Marks when the WBAccessCounter exceeds max value (oxff)
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reg WBInProgress_sync1; // Synchronizing WBInProgress
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reg WBInProgress_tck; // Synchronizing WBInProgress to tck clock signal
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wire trst;
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wire trst;
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [31:0] RegDataIn; // Data from registers (read data)
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Line 417... |
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
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assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
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{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
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{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
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assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
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assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
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assign Register_Data = {send_crc, DataReadLatch, 6'h0};
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assign Register_Data = {send_crc, DataReadLatch, 6'h0};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 31'h0, WBInProgress, WBErrorLatch};
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assign chain_sel_data = {send_crc, 4'h0};
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assign chain_sel_data = {send_crc, 4'h0};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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Line 589... |
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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RISCAccessTck <=#Tp 1'b1;
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RISCAccessTck <=#Tp 1'b1;
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end
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end
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else
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else
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if(WishboneScanChain)
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if(WishboneScanChain & (!WBInProgress_tck))
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begin
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begin
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ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
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ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
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RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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wb_AccessTck <=#Tp 1'b1; //
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wb_AccessTck <=#Tp 1'b1; //
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Line 673... |
always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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wb_cyc_o <=#Tp 1'b0;
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wb_cyc_o <=#Tp 1'b0;
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else
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else
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if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
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if(wb_Access_wbClk & ~wb_Access_wbClk_q)
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wb_cyc_o <=#Tp 1'b1;
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wb_cyc_o <=#Tp 1'b1;
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else
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else
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if(wb_ack_i | wb_err_i)
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if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
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wb_cyc_o <=#Tp 1'b0;
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wb_cyc_o <=#Tp 1'b0;
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end
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end
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assign wb_stb_o = wb_cyc_o;
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assign wb_stb_o = wb_cyc_o;
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Line 707... |
if(wb_ack_i)
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if(wb_ack_i)
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WBErrorLatch<=#Tp 1'b0; // Clearing status
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WBErrorLatch<=#Tp 1'b0; // Clearing status
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end
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end
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// WBInProgress is set at the beginning of the access and cleared when wb_ack_i or wb_err_i is set
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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WBInProgress<=#Tp 1'b0;
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else
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if(wb_Access_wbClk & ~wb_Access_wbClk_q)
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WBInProgress<=#Tp 1'b1;
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else
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if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
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WBInProgress<=#Tp 1'b0;
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end
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// Synchronizing WBInProgress
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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WBAccessCounter<=#Tp 8'h0;
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else
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if(wb_ack_i | wb_err_i | WBAccessCounterExceed)
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WBAccessCounter<=#Tp 8'h0;
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else
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if(wb_cyc_o)
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WBAccessCounter<=#Tp WBAccessCounter + 1'b1;
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end
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assign WBAccessCounterExceed = WBAccessCounter==8'hff;
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// Synchronizing WBInProgress
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always @ (posedge tck)
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begin
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WBInProgress_sync1<=#Tp WBInProgress;
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WBInProgress_tck<=#Tp WBInProgress_sync1;
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end
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// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
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// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
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assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
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`else
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`else
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assign risc_stall_o = RiscStall_access | RiscStall_reg;
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assign risc_stall_o = RiscStall_access | RiscStall_reg;
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