| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2003/08/28 13:55:22 simons
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// Three more chains added for cpu debug access.
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//
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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// Multiple cpu support added.
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//
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//
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// Revision 1.28 2002/11/06 14:22:41 mohor
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// Revision 1.28 2002/11/06 14:22:41 mohor
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// Trst signal is not inverted here any more. Inverted on higher layer !!!.
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// Trst signal is not inverted here any more. Inverted on higher layer !!!.
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| Line 416... |
Line 419... |
wire [73:0] RISC_Data;
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wire [73:0] RISC_Data;
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wire [46:0] Register_Data;
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wire [46:0] Register_Data;
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wire [73:0] WISHBONE_Data;
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wire [73:0] WISHBONE_Data;
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wire [12:0] chain_sel_data;
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wire [12:0] chain_sel_data;
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wire wb_Access_wbClk;
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wire wb_Access_wbClk;
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wire [1:0] wb_cntl_o;
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reg select_crc_out;
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reg select_crc_out;
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always @ (posedge tck or posedge trst)
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always @ (posedge tck or posedge trst)
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begin
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begin
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| Line 665... |
Line 669... |
RISCAccessTck3 <=#Tp 1'b0;
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RISCAccessTck3 <=#Tp 1'b0;
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end
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end
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end
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end
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assign wb_adr_o = ADDR;
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assign wb_adr_o = ADDR & {32{wb_cyc_o}};
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assign wb_we_o = RW;
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assign wb_we_o = RW & wb_cyc_o;
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assign wb_dat_o = DataOut;
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assign wb_dat_o = DataOut & {32{wb_cyc_o}};
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assign wb_sel_o[3:0] = 4'hf;
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assign wb_cab_o = 1'b0;
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assign wb_cab_o = 1'b0;
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reg [3:0] wb_sel_o;
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always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
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begin
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if(wb_cyc_o)
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case (wb_cntl_o)
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2'b00: wb_sel_o = 4'hf;
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2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
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2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
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default: wb_sel_o = 4'hf;
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endcase
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else
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wb_sel_o = 4'hf;
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end
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// Synchronizing the RegAccess signal to risc_clk_i clock
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// Synchronizing the RegAccess signal to risc_clk_i clock
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dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
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dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
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.set2(RegAccessTck), .sync_out(RegAccess)
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.set2(RegAccessTck), .sync_out(RegAccess)
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);
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);
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| Line 991... |
Line 1007... |
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
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.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
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`endif
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`endif
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.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
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.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
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.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
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.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o), .wb_cntl_o(wb_cntl_o)
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);
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);
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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