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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.34 2003/12/23 15:07:34 mohor
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// New directory structure. New version of the debug interface.
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// Files that are not needed removed.
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//
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// Revision 1.33 2003/10/23 16:17:01 mohor
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// Revision 1.33 2003/10/23 16:17:01 mohor
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// CRC logic changed.
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// CRC logic changed.
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//
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//
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// Revision 1.32 2003/09/18 14:00:47 simons
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// Revision 1.32 2003/09/18 14:00:47 simons
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// Lower two address lines must be always zero.
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// Lower two address lines must be always zero.
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Line 171... |
`include "dbg_defines.v"
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`include "dbg_defines.v"
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// Top module
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// Top module
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module dbg_top(
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module dbg_top(
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// JTAG signals
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// JTAG signals
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trst_i, // trst_i is active high (inverted on higher layers)
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tck_i,
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tck_i,
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tdi_i,
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tdi_i,
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tdo_o,
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tdo_o,
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// TAP states
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// TAP states
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Line 193... |
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
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wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
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);
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);
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// JTAG signals
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// JTAG signals
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input trst_i;
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input tck_i;
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input tck_i;
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input tdi_i;
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input tdi_i;
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output tdo_o;
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output tdo_o;
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// TAP states
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// TAP states
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| Line 251... |
Line 253... |
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reg tdo_o;
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reg tdo_o;
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reg wishbone_ce;
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reg wishbone_ce;
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// data counter
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// data counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if(shift_dr_i & (~data_cnt_end))
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else if(shift_dr_i & (~data_cnt_end))
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data_cnt <= #1 data_cnt + 1'b1;
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data_cnt <= #1 data_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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| Line 266... |
Line 268... |
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assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
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assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN;
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 'h0;
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
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else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select)
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crc_cnt <= #1 crc_cnt + 1'b1;
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crc_cnt <= #1 crc_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 'h0;
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Line 290... |
crc_cnt_end_q3 <= #1 crc_cnt_end_q2;
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crc_cnt_end_q3 <= #1 crc_cnt_end_q2;
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end
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end
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// status counter
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// status counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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status_cnt <= #1 'h0;
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status_cnt <= #1 'h0;
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
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status_cnt <= #1 status_cnt + 1'b1;
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status_cnt <= #1 status_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt <= #1 'h0;
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status_cnt <= #1 'h0;
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| Line 304... |
Line 306... |
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assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
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assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i;
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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chain_select <= #1 1'b0;
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chain_select <= #1 1'b0;
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else if(selecting_command & tdi_i) // Chain select
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else if(selecting_command & tdi_i) // Chain select
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chain_select <= #1 1'b1;
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chain_select <= #1 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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chain_select <= #1 1'b0;
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chain_select <= #1 1'b0;
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| Line 329... |
Line 331... |
default : chain_select_error <= #1 1'b1;
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default : chain_select_error <= #1 1'b1;
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endcase
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endcase
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end
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end
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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chain <= `CHAIN_ID_LENGTH'b111;
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chain <= `CHAIN_ID_LENGTH'b111;
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else if(chain_select & crc_cnt_end & (~crc_cnt_end_q) & crc_match)
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else if(chain_select & crc_cnt_end & (~crc_cnt_end_q) & crc_match)
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chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
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chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
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end
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end
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| Line 354... |
Line 356... |
dbg_crc32_d1 i_dbg_crc32_d1_in
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dbg_crc32_d1 i_dbg_crc32_d1_in
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(
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(
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.data (tdi_i),
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.data (tdi_i),
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.enable (shift_dr_i),
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.enable (shift_dr_i),
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.shift (1'b0),
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.shift (1'b0),
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.rst (trst_i),
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.rst (wb_rst_i),
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.sync_rst (update_dr_i),
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.sync_rst (update_dr_i),
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.crc_out (),
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.crc_out (),
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.clk (tck_i),
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.clk (tck_i),
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.crc_match (crc_match)
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.crc_match (crc_match)
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);
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);
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| Line 388... |
Line 390... |
(
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(
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.data (tdo_tmp),
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.data (tdo_tmp),
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.enable (crc_en), // enable has priority
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.enable (crc_en), // enable has priority
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// .shift (1'b0),
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// .shift (1'b0),
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.shift (shift_dr_i & crc_started & (~crc_en)),
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.shift (shift_dr_i & crc_started & (~crc_en)),
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.rst (trst_i),
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.rst (wb_rst_i),
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.sync_rst (update_dr_i),
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.sync_rst (update_dr_i),
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.crc_out (crc_out),
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.crc_out (crc_out),
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.clk (tck_i),
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.clk (tck_i),
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.crc_match ()
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.crc_match ()
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);
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);
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Line 458... |
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// Signals for WISHBONE module
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// Signals for WISHBONE module
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (trst_i)
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if (wb_rst_i)
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wishbone_ce <= #1 1'b0;
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wishbone_ce <= #1 1'b0;
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else if(selecting_command & (~tdi_i) & wishbone_scan_chain) // wishbone CE
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else if(selecting_command & (~tdi_i) & wishbone_scan_chain) // wishbone CE
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wishbone_ce <= #1 1'b1;
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wishbone_ce <= #1 1'b1;
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else if (update_dr_i) // igor !!! This needs to be changed?
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else if (update_dr_i) // igor !!! This needs to be changed?
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wishbone_ce <= #1 1'b0;
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wishbone_ce <= #1 1'b0;
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| Line 472... |
Line 474... |
assign tdi_wb = wishbone_ce & tdi_i;
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assign tdi_wb = wishbone_ce & tdi_i;
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// Connecting wishbone module
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// Connecting wishbone module
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dbg_wb i_dbg_wb (
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dbg_wb i_dbg_wb (
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// JTAG signals
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// JTAG signals
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.trst_i (trst_i), // trst_i is active high (inverted on higher layers)
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.tck_i (tck_i),
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.tck_i (tck_i),
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.tdi_i (tdi_wb),
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.tdi_i (tdi_wb),
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.tdo_o (tdo_wb),
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.tdo_o (tdo_wb),
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// TAP states
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// TAP states
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| Line 486... |
Line 487... |
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.wishbone_ce_i (wishbone_ce),
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.wishbone_ce_i (wishbone_ce),
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.crc_match_i (crc_match),
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.crc_match_i (crc_match),
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.crc_en_o (crc_en_wb),
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.crc_en_o (crc_en_wb),
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.shift_crc_o (shift_crc_wb),
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.shift_crc_o (shift_crc_wb),
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.rst_i (wb_rst_i),
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// WISHBONE common signals
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// WISHBONE common signals
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.wb_rst_i (wb_rst_i),
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.wb_clk_i (wb_clk_i),
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.wb_clk_i (wb_clk_i),
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// WISHBONE master interface
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// WISHBONE master interface
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.wb_adr_o (wb_adr_o),
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.wb_adr_o (wb_adr_o),
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.wb_dat_o (wb_dat_o),
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.wb_dat_o (wb_dat_o),
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