| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.16 2004/01/19 07:32:41 simons
|
|
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
|
|
//
|
// Revision 1.15 2004/01/17 18:01:24 mohor
|
// Revision 1.15 2004/01/17 18:01:24 mohor
|
// New version.
|
// New version.
|
//
|
//
|
// Revision 1.14 2004/01/16 14:51:33 mohor
|
// Revision 1.14 2004/01/16 14:51:33 mohor
|
// cpu registers added.
|
// cpu registers added.
|
| Line 270... |
Line 273... |
ptr <= ptr + 1'd1;
|
ptr <= ptr + 1'd1;
|
end
|
end
|
|
|
|
|
// Shift register for shifting in and out the data
|
// Shift register for shifting in and out the data
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (read_cycle & crc_cnt_31)
|
if (rst_i)
|
|
begin
|
|
dr <= #1 51'h0;
|
|
latch_data <= #1 1'b0;
|
|
end
|
|
else if (read_cycle & crc_cnt_31)
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
|
dr[31:0] <= #1 input_data[31:0];
|
latch_data <= #1 1'b1;
|
latch_data <= #1 1'b1;
|
end
|
end
|
else if (read_cycle & crc_cnt_end)
|
else if (read_cycle & crc_cnt_end)
|
| Line 669... |
Line 677... |
else if (cmd_read & go_prelim)
|
else if (cmd_read & go_prelim)
|
read_cycle <= #1 1'b1;
|
read_cycle <= #1 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if ((cmd_read | cmd_write) & go_prelim)
|
if (rst_i)
|
|
rw_type <= #1 3'h0;
|
|
else if ((cmd_read | cmd_write) & go_prelim)
|
rw_type <= #1 cmd;
|
rw_type <= #1 cmd;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
write_cycle <= #1 1'b0;
|
|
else if (update_dr_i)
|
write_cycle <= #1 1'b0;
|
write_cycle <= #1 1'b0;
|
else if (cmd_write & go_prelim)
|
else if (cmd_write & go_prelim)
|
write_cycle <= #1 1'b1;
|
write_cycle <= #1 1'b1;
|
end
|
end
|
|
|
|
|
// Start wishbone write cycle
|
// Start wishbone write cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
begin
|
begin
|
if (write_cycle)
|
start_wr_tck <= #1 1'b0;
|
|
wb_dat_o <= #1 32'h0;
|
|
end
|
|
else if (write_cycle)
|
begin
|
begin
|
case (rw_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_WRITE8 : begin
|
`WB_WRITE8 : begin
|
if (byte_q & (~byte_q2))
|
if (byte_q & (~byte_q2))
|
begin
|
begin
|
| Line 760... |
Line 777... |
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
end
|
end
|
|
|
|
|
// wb_adr_o logic
|
// wb_adr_o logic
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
if (rst_i)
|
|
wb_adr_o <= #1 32'h0;
|
|
else if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
wb_adr_o <= #1 adr;
|
wb_adr_o <= #1 adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
|
if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
