| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.17 2004/01/22 13:58:53 mohor
|
|
// Port signals are all set to zero after reset.
|
|
//
|
// Revision 1.16 2004/01/19 07:32:41 simons
|
// Revision 1.16 2004/01/19 07:32:41 simons
|
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
|
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
|
//
|
//
|
// Revision 1.15 2004/01/17 18:01:24 mohor
|
// Revision 1.15 2004/01/17 18:01:24 mohor
|
// New version.
|
// New version.
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| Line 261... |
Line 264... |
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
|
|
|
|
// Selecting where to take the data from
|
// Selecting where to take the data from
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
ptr <= #1 2'h0;
|
|
else if (update_dr_i)
|
ptr <= #1 2'h0;
|
ptr <= #1 2'h0;
|
else if (read_cycle & crc_cnt_31) // first latch
|
else if (read_cycle & crc_cnt_31) // first latch
|
ptr <= #1 ptr + 1'b1;
|
ptr <= #1 ptr + 1'b1;
|
else if (read_cycle & byte & (~byte_q))
|
else if (read_cycle & byte & (~byte_q))
|
ptr <= ptr + 1'd1;
|
ptr <= ptr + 1'd1;
|
| Line 393... |
Line 398... |
assign byte = data_cnt[2:0] == 3'd7;
|
assign byte = data_cnt[2:0] == 3'd7;
|
assign half = data_cnt[3:0] == 4'd15;
|
assign half = data_cnt[3:0] == 4'd15;
|
assign long = data_cnt[4:0] == 5'd31;
|
assign long = data_cnt[4:0] == 5'd31;
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
byte_q <= #1 1'b0;
|
|
half_q <= #1 1'b0;
|
|
long_q <= #1 1'b0;
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|
byte_q2 <= #1 1'b0;
|
|
half_q2 <= #1 1'b0;
|
|
long_q2 <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
byte_q <= #1 byte;
|
byte_q <= #1 byte;
|
half_q <= #1 half;
|
half_q <= #1 half;
|
long_q <= #1 long;
|
long_q <= #1 long;
|
byte_q2 <= #1 byte_q;
|
byte_q2 <= #1 byte_q;
|
half_q2 <= #1 half_q;
|
half_q2 <= #1 half_q;
|
long_q2 <= #1 long_q;
|
long_q2 <= #1 long_q;
|
end
|
end
|
|
end
|
|
|
|
|
assign dr_read = (dr[2:0] == `WB_READ8) || (dr[2:0] == `WB_READ16) || (dr[2:0] == `WB_READ32);
|
assign dr_read = (dr[2:0] == `WB_READ8) || (dr[2:0] == `WB_READ16) || (dr[2:0] == `WB_READ32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) || (dr[2:0] == `WB_WRITE16) || (dr[2:0] == `WB_WRITE32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) || (dr[2:0] == `WB_WRITE16) || (dr[2:0] == `WB_WRITE32);
|
assign dr_go = dr[2:0] == `WB_GO;
|
assign dr_go = dr[2:0] == `WB_GO;
|
|
|
|
|
// Latching instruction
|
// Latching instruction
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
begin
|
|
dr_cmd_latched <= #1 3'h0;
|
|
dr_read_latched <= #1 1'b0;
|
|
dr_write_latched <= #1 1'b0;
|
|
dr_go_latched <= #1 1'b0;
|
|
end
|
|
else if (update_dr_i)
|
begin
|
begin
|
dr_cmd_latched <= #1 3'h0;
|
dr_cmd_latched <= #1 3'h0;
|
dr_read_latched <= #1 1'b0;
|
dr_read_latched <= #1 1'b0;
|
dr_write_latched <= #1 1'b0;
|
dr_write_latched <= #1 1'b0;
|
dr_go_latched <= #1 1'b0;
|
dr_go_latched <= #1 1'b0;
|
| Line 430... |
Line 454... |
end
|
end
|
end
|
end
|
|
|
|
|
// Upper limit. Address/length counter counts until this value is reached
|
// Upper limit. Address/length counter counts until this value is reached
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (cmd_cnt == 2'h2)
|
if (rst_i)
|
|
addr_len_cnt_limit <= #1 6'd0;
|
|
else if (cmd_cnt == 2'h2)
|
begin
|
begin
|
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
|
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
|
addr_len_cnt_limit <= #1 6'd0;
|
addr_len_cnt_limit <= #1 6'd0;
|
else // (current command is WB_WRITEx or WB_READx)
|
else // (current command is WB_WRITEx or WB_READx)
|
addr_len_cnt_limit <= #1 6'd48;
|
addr_len_cnt_limit <= #1 6'd48;
|
| Line 446... |
Line 472... |
|
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
|
|
|
|
// Upper limit. Data counter counts until this value is reached.
|
// Upper limit. Data counter counts until this value is reached.
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
data_cnt_limit <= #1 19'h0;
|
|
else if (update_dr_i)
|
data_cnt_limit <= #1 {len, 3'b000};
|
data_cnt_limit <= #1 {len, 3'b000};
|
end
|
end
|
|
|
|
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
| Line 473... |
Line 501... |
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
assign crc_cnt_end = crc_cnt == 6'd32;
|
assign crc_cnt_31 = crc_cnt == 6'd31;
|
assign crc_cnt_31 = crc_cnt == 6'd31;
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
assign data_cnt_end = (data_cnt == data_cnt_limit);
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
crc_cnt_end_q <= #1 1'b0;
|
|
cmd_cnt_end_q <= #1 1'b0;
|
|
data_cnt_end_q <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
data_cnt_end_q <= #1 data_cnt_end;
|
data_cnt_end_q <= #1 data_cnt_end;
|
end
|
end
|
|
end
|
|
|
|
|
// Status counter is made of 4 serialy connected registers
|
// Status counter is made of 4 serialy connected registers
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
| Line 581... |
Line 618... |
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
if (rst_i)
|
|
crc_match_reg <= #1 1'b0;
|
|
else if(crc_cnt_end & (~crc_cnt_end_q))
|
crc_match_reg <= #1 crc_match_i;
|
crc_match_reg <= #1 crc_match_i;
|
end
|
end
|
|
|
|
|
// Latching instruction
|
// Latching instruction
|
| Line 611... |
Line 650... |
end
|
end
|
end
|
end
|
|
|
|
|
// Latching address
|
// Latching address
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
if (rst_i)
|
|
begin
|
|
adr <= #1 32'h0;
|
|
set_addr <= #1 1'b0;
|
|
end
|
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
if (dr_write_latched | dr_read_latched)
|
if (dr_write_latched | dr_read_latched)
|
begin
|
begin
|
adr <= #1 dr[47:16];
|
adr <= #1 dr[47:16];
|
set_addr <= #1 1'b1;
|
set_addr <= #1 1'b1;
|
| Line 627... |
Line 671... |
set_addr <= #1 1'b0;
|
set_addr <= #1 1'b0;
|
end
|
end
|
|
|
|
|
// Length counter
|
// Length counter
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
if (rst_i)
|
|
len <= #1 16'h0;
|
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
len <= #1 dr[15:0];
|
len <= #1 dr[15:0];
|
else if (start_rd_tck)
|
else if (start_rd_tck)
|
begin
|
begin
|
case (rw_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : len <= #1 len - 1'd1;
|
`WB_READ8 : len <= #1 len - 1'd1;
|
| Line 646... |
Line 692... |
|
|
assign len_eq_0 = len == 16'h0;
|
assign len_eq_0 = len == 16'h0;
|
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
|
if (rst_i)
|
|
start_rd_tck <= #1 1'b0;
|
|
else if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started))
|
else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started))
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else
|
else
|
start_rd_tck <= #1 1'b0;
|
start_rd_tck <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
rd_tck_started <= #1 1'b0;
|
|
else if (update_dr_i)
|
rd_tck_started <= #1 1'b0;
|
rd_tck_started <= #1 1'b0;
|
else if (start_rd_tck)
|
else if (start_rd_tck)
|
rd_tck_started <= #1 1'b1;
|
rd_tck_started <= #1 1'b1;
|
else if (wb_end_tck & (~wb_end_tck_q))
|
else if (wb_end_tck & (~wb_end_tck_q))
|
rd_tck_started <= #1 1'b0;
|
rd_tck_started <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (rst_i)
|
|
read_cycle <= #1 1'b0;
|
|
else if (update_dr_i)
|
read_cycle <= #1 1'b0;
|
read_cycle <= #1 1'b0;
|
else if (cmd_read & go_prelim)
|
else if (cmd_read & go_prelim)
|
read_cycle <= #1 1'b1;
|
read_cycle <= #1 1'b1;
|
end
|
end
|
|
|
| Line 748... |
Line 800... |
else
|
else
|
start_wr_tck <= #1 1'b0;
|
start_wr_tck <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
start_rd_sync1 <= #1 1'b0;
|
|
start_wb_rd <= #1 1'b0;
|
|
start_wb_rd_q <= #1 1'b0;
|
|
|
|
start_wr_sync1 <= #1 1'b0;
|
|
start_wb_wr <= #1 1'b0;
|
|
start_wb_wr_q <= #1 1'b0;
|
|
|
|
set_addr_sync <= #1 1'b0;
|
|
set_addr_wb <= #1 1'b0;
|
|
set_addr_wb_q <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
start_rd_sync1 <= #1 start_rd_tck;
|
start_rd_sync1 <= #1 start_rd_tck;
|
start_wb_rd <= #1 start_rd_sync1;
|
start_wb_rd <= #1 start_rd_sync1;
|
start_wb_rd_q <= #1 start_wb_rd;
|
start_wb_rd_q <= #1 start_wb_rd;
|
|
|
| Line 762... |
Line 830... |
|
|
set_addr_sync <= #1 set_addr;
|
set_addr_sync <= #1 set_addr;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb_q <= #1 set_addr_wb;
|
set_addr_wb_q <= #1 set_addr_wb;
|
end
|
end
|
|
end
|
|
|
|
|
// wb_cyc_o
|
// wb_cyc_o
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
| Line 879... |
Line 948... |
busy_tck <= #1 busy_sync;
|
busy_tck <= #1 busy_sync;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
wb_end_rst_sync <= #1 1'b0;
|
|
wb_end_rst <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
end
|
end
|
|
end
|
|
|
|
|
// Detecting WB error
|
// Detecting WB error
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
| Line 898... |
Line 975... |
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
wb_error_sync <= #1 1'b0;
|
|
wb_error_tck <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
wb_error_sync <= #1 wb_error;
|
wb_error_sync <= #1 wb_error;
|
wb_error_tck <= #1 wb_error_sync;
|
wb_error_tck <= #1 wb_error_sync;
|
end
|
end
|
|
end
|
|
|
|
|
// Detecting overrun when write operation.
|
// Detecting overrun when write operation.
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
| Line 916... |
Line 1001... |
wb_overrun <= #1 1'b1;
|
wb_overrun <= #1 1'b1;
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
end
|
end
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
wb_overrun_sync <= #1 1'b0;
|
|
wb_overrun_tck <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
wb_overrun_sync <= #1 wb_overrun;
|
wb_overrun_sync <= #1 wb_overrun;
|
wb_overrun_tck <= #1 wb_overrun_sync;
|
wb_overrun_tck <= #1 wb_overrun_sync;
|
end
|
end
|
|
end
|
|
|
|
|
// Detecting underrun when read operation
|
// Detecting underrun when read operation
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
| Line 948... |
Line 1041... |
else
|
else
|
status_reset_en <= #1 1'b0;
|
status_reset_en <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
begin
|
|
wishbone_ce_sync <= #1 1'b0;
|
|
wishbone_ce_rst <= #1 1'b0;
|
|
end
|
|
else
|
begin
|
begin
|
wishbone_ce_sync <= #1 wishbone_ce_i;
|
wishbone_ce_sync <= #1 wishbone_ce_i;
|
wishbone_ce_rst <= #1 ~wishbone_ce_sync;
|
wishbone_ce_rst <= #1 ~wishbone_ce_sync;
|
end
|
end
|
|
end
|
|
|
|
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// Logic for latching data that is read from wishbone
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// Logic for latching data that is read from wishbone
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i or posedge rst_i)
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begin
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begin
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if(wishbone_ce_rst)
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if (rst_i)
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mem_ptr <= #1 3'h0;
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else if(wishbone_ce_rst)
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mem_ptr <= #1 3'h0;
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mem_ptr <= #1 3'h0;
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else if (wb_ack_i)
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else if (wb_ack_i)
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begin
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begin
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if (rw_type == `WB_READ8)
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if (rw_type == `WB_READ8)
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mem_ptr <= #1 mem_ptr + 1'd1;
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mem_ptr <= #1 mem_ptr + 1'd1;
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| Line 1007... |
Line 1110... |
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assign input_data = {mem[0], mem[1], mem[2], mem[3]};
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assign input_data = {mem[0], mem[1], mem[2], mem[3]};
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// Fifo counter and empty/full detection
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// Fifo counter and empty/full detection
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always @ (posedge tck_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (update_dr_i)
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if (rst_i)
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fifo_cnt <= #1 3'h0;
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else if (update_dr_i)
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fifo_cnt <= #1 3'h0;
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fifo_cnt <= #1 3'h0;
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else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
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else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
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begin
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begin
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case (rw_type) // synthesis parallel_case full_case
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case (rw_type) // synthesis parallel_case full_case
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`WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
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`WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
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