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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 - 2003 Authors ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.18 2004/01/25 14:04:18 mohor
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// All flipflops are reset.
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//
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// Revision 1.17 2004/01/22 13:58:53 mohor
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// Revision 1.17 2004/01/22 13:58:53 mohor
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// Port signals are all set to zero after reset.
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// Port signals are all set to zero after reset.
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//
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//
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// Revision 1.16 2004/01/19 07:32:41 simons
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// Revision 1.16 2004/01/19 07:32:41 simons
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
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Line 172... |
reg tdo_o;
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reg tdo_o;
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reg [50:0] dr;
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reg [50:0] dr;
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wire enable;
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wire enable;
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wire cmd_cnt_en;
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wire cmd_cnt_en;
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reg [1:0] cmd_cnt;
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reg [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;
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wire cmd_cnt_end;
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wire cmd_cnt_end;
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reg cmd_cnt_end_q;
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reg cmd_cnt_end_q;
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wire addr_len_cnt_en;
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wire addr_len_cnt_en;
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reg [5:0] addr_len_cnt;
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reg [5:0] addr_len_cnt;
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reg [5:0] addr_len_cnt_limit;
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reg [5:0] addr_len_cnt_limit;
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| Line 221... |
Line 224... |
reg cmd_write;
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reg cmd_write;
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reg cmd_go;
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reg cmd_go;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg [`STATUS_LEN -1:0] status;
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reg [`DBG_WB_STATUS_LEN -1:0] status;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
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reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
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reg underrun_tck;
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reg underrun_tck;
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Line 357... |
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// Command counter
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// Command counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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cmd_cnt <= #1 2'h0;
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cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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else if (update_dr_i)
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else if (update_dr_i)
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cmd_cnt <= #1 2'h0;
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cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
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else if (cmd_cnt_en)
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else if (cmd_cnt_en)
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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end
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end
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Line 461... |
// Upper limit. Address/length counter counts until this value is reached
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// Upper limit. Address/length counter counts until this value is reached
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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addr_len_cnt_limit <= #1 6'd0;
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addr_len_cnt_limit <= #1 6'd0;
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else if (cmd_cnt == 2'h2)
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else if (cmd_cnt == `DBG_WB_CMD_CNT_WIDTH'h2)
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begin
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begin
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if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
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if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
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addr_len_cnt_limit <= #1 6'd0;
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addr_len_cnt_limit <= #1 6'd0;
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else // (current command is WB_WRITEx or WB_READx)
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else // (current command is WB_WRITEx or WB_READx)
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addr_len_cnt_limit <= #1 6'd48;
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addr_len_cnt_limit <= #1 6'd48;
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Line 498... |
crc_cnt <= #1 crc_cnt + 1'b1;
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crc_cnt <= #1 crc_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= #1 6'h0;
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crc_cnt <= #1 6'h0;
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end
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end
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign cmd_cnt_end = cmd_cnt == `DBG_WB_CMD_LEN;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_31 = crc_cnt == 6'd31;
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assign crc_cnt_31 = crc_cnt == 6'd31;
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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Line 566... |
// Status register
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// Status register
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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status <= #1 {`STATUS_LEN{1'b0}};
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status <= #1 {`DBG_WB_STATUS_LEN{1'b0}};
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end
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end
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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begin
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begin
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status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
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status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
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end
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end
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Line 578... |
begin
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begin
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status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
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status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
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end
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end
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else if (shift_dr_i & (~status_cnt_end))
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else if (shift_dr_i & (~status_cnt_end))
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begin
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begin
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status <= #1 {status[0], status[`STATUS_LEN -1:1]};
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status <= #1 {status[0], status[`DBG_WB_STATUS_LEN -1:1]};
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end
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end
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end
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end
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// Following status is shifted out:
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// Following status is shifted out:
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// 1. bit: 1 if crc is OK, else 0
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// 1. bit: 1 if crc is OK, else 0
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// 2. bit: 1 while WB access is in progress (busy_tck), else 0
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// 2. bit: 1 while WB access is in progress (busy_tck), else 0
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