| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.21 2004/03/31 14:34:09 igorm
|
|
// data_cnt_lim length changed to reduce number of warnings.
|
|
//
|
// Revision 1.20 2004/03/28 20:27:02 igorm
|
// Revision 1.20 2004/03/28 20:27:02 igorm
|
// New release of the debug interface (3rd. release).
|
// New release of the debug interface (3rd. release).
|
//
|
//
|
// Revision 1.19 2004/03/22 16:35:46 igorm
|
// Revision 1.19 2004/03/22 16:35:46 igorm
|
// Temp version before changing dbg interface.
|
// Temp version before changing dbg interface.
|
| Line 247... |
Line 250... |
|
|
reg [1:0] ptr;
|
reg [1:0] ptr;
|
reg [2:0] fifo_cnt;
|
reg [2:0] fifo_cnt;
|
wire fifo_full;
|
wire fifo_full;
|
wire fifo_empty;
|
wire fifo_empty;
|
reg [7:0] mem [0:3];
|
//reg [7:0] mem [0:3];
|
|
reg [7:0] mem0, mem1, mem2, mem3;
|
reg [2:0] mem_ptr_dsff;
|
reg [2:0] mem_ptr_dsff;
|
reg wishbone_ce_csff;
|
reg wishbone_ce_csff;
|
reg mem_ptr_init;
|
reg mem_ptr_init;
|
reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
|
reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
|
wire curr_cmd_go;
|
wire curr_cmd_go;
|
| Line 293... |
Line 297... |
else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
|
else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
|
ptr <= ptr + 1'd1;
|
ptr <= ptr + 1'd1;
|
end
|
end
|
|
|
|
|
reg [799:0] dr_text;
|
|
// Shift register for shifting in and out the data
|
// Shift register for shifting in and out the data
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
latch_data <= #1 1'b0;
|
latch_data <= #1 1'b0;
|
dr <= #1 {`DBG_WB_DR_LEN{1'b0}};
|
dr <= #1 {`DBG_WB_DR_LEN{1'b0}};
|
dr_text = "reset";
|
|
end
|
end
|
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
|
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
|
begin
|
begin
|
dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
|
dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
|
dr_text = "latch reg data";
|
|
end
|
end
|
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
|
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
|
dr[31:0] <= #1 input_data[31:0];
|
latch_data <= #1 1'b1;
|
latch_data <= #1 1'b1;
|
dr_text = "latch first data";
|
|
end
|
end
|
else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
|
else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case full_case
|
case (acc_type) // synthesis parallel_case full_case
|
`DBG_WB_READ8 : begin
|
`DBG_WB_READ8 : begin
|
| Line 327... |
Line 327... |
2'b01 : dr[31:24] <= #1 input_data[23:16];
|
2'b01 : dr[31:24] <= #1 input_data[23:16];
|
2'b10 : dr[31:24] <= #1 input_data[15:8];
|
2'b10 : dr[31:24] <= #1 input_data[15:8];
|
2'b11 : dr[31:24] <= #1 input_data[7:0];
|
2'b11 : dr[31:24] <= #1 input_data[7:0];
|
endcase
|
endcase
|
latch_data <= #1 1'b1;
|
latch_data <= #1 1'b1;
|
dr_text = "latch_data byte";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:24] <= #1 {dr[30:24], 1'b0};
|
dr[31:24] <= #1 {dr[30:24], 1'b0};
|
latch_data <= #1 1'b0;
|
latch_data <= #1 1'b0;
|
dr_text = "shift byte";
|
|
end
|
end
|
end
|
end
|
`DBG_WB_READ16: begin
|
`DBG_WB_READ16: begin
|
if(half & (~half_q))
|
if(half & (~half_q))
|
begin
|
begin
|
if (ptr[1])
|
if (ptr[1])
|
dr[31:16] <= #1 input_data[15:0];
|
dr[31:16] <= #1 input_data[15:0];
|
else
|
else
|
dr[31:16] <= #1 input_data[31:16];
|
dr[31:16] <= #1 input_data[31:16];
|
latch_data <= #1 1'b1;
|
latch_data <= #1 1'b1;
|
dr_text = "latch_data_half";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:16] <= #1 {dr[30:16], 1'b0};
|
dr[31:16] <= #1 {dr[30:16], 1'b0};
|
latch_data <= #1 1'b0;
|
latch_data <= #1 1'b0;
|
dr_text = "shift half";
|
|
end
|
end
|
end
|
end
|
`DBG_WB_READ32: begin
|
`DBG_WB_READ32: begin
|
if(long & (~long_q))
|
if(long & (~long_q))
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
|
dr[31:0] <= #1 input_data[31:0];
|
latch_data <= #1 1'b1;
|
latch_data <= #1 1'b1;
|
dr_text = "latch_data word";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
latch_data <= #1 1'b0;
|
latch_data <= #1 1'b0;
|
dr_text = "shift word";
|
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
else if (enable && (!addr_len_cnt_end))
|
else if (enable && (!addr_len_cnt_end))
|
begin
|
begin
|
dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
|
dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
|
dr_text = "shift dr";
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
| Line 1023... |
Line 1016... |
mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
|
mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
/* Logic for latching data that is read from wishbone
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if (wb_ack_i)
|
|
begin
|
|
case (wb_sel_dsff) // synthesis parallel_case full_case
|
|
4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte
|
|
4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte
|
|
4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte
|
|
4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte
|
|
|
|
4'b1100 : // half
|
|
begin
|
|
mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
|
|
mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
|
|
end
|
|
4'b0011 : // half
|
|
begin
|
|
mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
|
|
mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
|
|
end
|
|
4'b1111 : // long
|
|
begin
|
|
mem[0] <= #1 wb_dat_i[31:24];
|
|
mem[1] <= #1 wb_dat_i[23:16];
|
|
mem[2] <= #1 wb_dat_i[15:08];
|
|
mem[3] <= #1 wb_dat_i[07:00];
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
*/
|
|
|
// Logic for latching data that is read from wishbone
|
// Logic for latching data that is read from wishbone
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if (wb_ack_i)
|
if (wb_ack_i)
|
begin
|
begin
|
case (wb_sel_dsff) // synthesis parallel_case full_case
|
case (wb_sel_dsff) // synthesis parallel_case full_case
|
4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte
|
4'b1000 : begin
|
4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte
|
2'b00: mem0 <= #1 wb_dat_i[31:24];
|
4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte
|
2'b01: mem1 <= #1 wb_dat_i[31:24];
|
|
2'b10: mem2 <= #1 wb_dat_i[31:24];
|
|
2'b11: mem3 <= #1 wb_dat_i[31:24];
|
|
endcase
|
|
end
|
|
4'b0100 : begin
|
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem0 <= #1 wb_dat_i[23:16];
|
|
2'b01: mem1 <= #1 wb_dat_i[23:16];
|
|
2'b10: mem2 <= #1 wb_dat_i[23:16];
|
|
2'b11: mem3 <= #1 wb_dat_i[23:16];
|
|
endcase
|
|
end
|
|
4'b0010 : begin
|
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem0 <= #1 wb_dat_i[15:08];
|
|
2'b01: mem1 <= #1 wb_dat_i[15:08];
|
|
2'b10: mem2 <= #1 wb_dat_i[15:08];
|
|
2'b11: mem3 <= #1 wb_dat_i[15:08];
|
|
endcase
|
|
end
|
|
4'b0001 : begin
|
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem0 <= #1 wb_dat_i[07:00];
|
|
2'b01: mem1 <= #1 wb_dat_i[07:00];
|
|
2'b10: mem2 <= #1 wb_dat_i[07:00];
|
|
2'b11: mem3 <= #1 wb_dat_i[07:00];
|
|
endcase
|
|
end
|
|
|
4'b1100 : // half
|
4'b1100 : // half
|
begin
|
begin
|
mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
|
2'b00: mem0 <= #1 wb_dat_i[31:24];
|
|
2'b01: mem1 <= #1 wb_dat_i[31:24];
|
|
2'b10: mem2 <= #1 wb_dat_i[31:24];
|
|
2'b11: mem3 <= #1 wb_dat_i[31:24];
|
|
endcase
|
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem1 <= #1 wb_dat_i[23:16];
|
|
2'b01: mem2 <= #1 wb_dat_i[23:16];
|
|
2'b10: mem3 <= #1 wb_dat_i[23:16];
|
|
2'b11: mem0 <= #1 wb_dat_i[23:16];
|
|
endcase
|
end
|
end
|
4'b0011 : // half
|
4'b0011 : // half
|
begin
|
begin
|
mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
|
2'b00: mem0 <= #1 wb_dat_i[15:08];
|
|
2'b01: mem1 <= #1 wb_dat_i[15:08];
|
|
2'b10: mem2 <= #1 wb_dat_i[15:08];
|
|
2'b11: mem3 <= #1 wb_dat_i[15:08];
|
|
endcase
|
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem1 <= #1 wb_dat_i[07:00];
|
|
2'b01: mem2 <= #1 wb_dat_i[07:00];
|
|
2'b10: mem3 <= #1 wb_dat_i[07:00];
|
|
2'b11: mem0 <= #1 wb_dat_i[07:00];
|
|
endcase
|
end
|
end
|
4'b1111 : // long
|
4'b1111 : // long
|
begin
|
begin
|
mem[0] <= #1 wb_dat_i[31:24];
|
mem0 <= #1 wb_dat_i[31:24];
|
mem[1] <= #1 wb_dat_i[23:16];
|
mem1 <= #1 wb_dat_i[23:16];
|
mem[2] <= #1 wb_dat_i[15:08];
|
mem2 <= #1 wb_dat_i[15:08];
|
mem[3] <= #1 wb_dat_i[07:00];
|
mem3 <= #1 wb_dat_i[07:00];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
//assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
assign input_data = {mem0, mem1, mem2, mem3};
|
|
|
|
|
// Fifo counter and empty/full detection
|
// Fifo counter and empty/full detection
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
| Line 1088... |
Line 1163... |
|
|
|
|
assign fifo_full = fifo_cnt == 3'h4;
|
assign fifo_full = fifo_cnt == 3'h4;
|
assign fifo_empty = fifo_cnt == 3'h0;
|
assign fifo_empty = fifo_cnt == 3'h0;
|
|
|
reg [799:0] tdo_text;
|
|
|
|
// TDO multiplexer
|
// TDO multiplexer
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
|
curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
|
curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
|
or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
|
or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
|
or addr_len_cnt_end or addr_len_cnt_end_q)
|
or addr_len_cnt_end or addr_len_cnt_end_q)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
tdo_text = "busy_tck";
|
|
end
|
end
|
else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
|
else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
|
begin
|
begin
|
tdo_o = ~crc_match_i;
|
tdo_o = ~crc_match_i;
|
tdo_text = "crc_match_i";
|
|
end
|
end
|
else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
|
else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
|
begin
|
begin
|
tdo_o = dr[31];
|
tdo_o = dr[31];
|
tdo_text = "dr[31]";
|
|
end
|
end
|
else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
|
else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
|
begin
|
begin
|
tdo_o = ~crc_match_reg;
|
tdo_o = ~crc_match_reg;
|
tdo_text = "crc_match_reg";
|
|
end
|
end
|
else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
|
else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
|
begin
|
begin
|
tdo_o = ~crc_match_reg;
|
tdo_o = ~crc_match_reg;
|
tdo_text = "crc_match_reg_rd_comm";
|
|
end
|
end
|
else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
|
else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
|
begin
|
begin
|
tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
|
tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
|
tdo_text = "rd_comm data";
|
|
end
|
end
|
else if (status_cnt_en)
|
else if (status_cnt_en)
|
begin
|
begin
|
tdo_o = status[3];
|
tdo_o = status[3];
|
tdo_text = "status";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tdo_o = 1'b0;
|
tdo_o = 1'b0;
|
tdo_text = "zero";
|
|
end
|
end
|
end
|
end
|
|
|
reg [799:0] status_text;
|
|
// Status register
|
// Status register
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
status <= #1 {`DBG_WB_STATUS_LEN{1'b0}};
|
status <= #1 {`DBG_WB_STATUS_LEN{1'b0}};
|
status_text = "reset";
|
|
end
|
end
|
else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
|
else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
|
begin
|
begin
|
status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
|
status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
|
status_text = "latch ni read";
|
|
end
|
end
|
else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
|
else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
|
begin
|
begin
|
status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
|
status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
|
status_text = "latch read";
|
|
end
|
end
|
else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
|
else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
|
begin
|
begin
|
status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
|
status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
|
status_text = "rd_comm";
|
|
end
|
end
|
else if (shift_dr_i && (!status_cnt_end))
|
else if (shift_dr_i && (!status_cnt_end))
|
begin
|
begin
|
status <= #1 {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
|
status <= #1 {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
|
status_text = "shifting";
|
|
end
|
end
|
end
|
end
|
// Following status is shifted out (MSB first):
|
// Following status is shifted out (MSB first):
|
// 3. bit: 1 if crc is OK, else 0
|
// 3. bit: 1 if crc is OK, else 0
|
// 2. bit: 1'b0
|
// 2. bit: 1'b0
|
