| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.22 2004/04/01 11:56:59 igorm
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// Port names and defines for the supported CPUs changed.
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//
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// Revision 1.21 2004/03/31 14:34:09 igorm
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// Revision 1.21 2004/03/31 14:34:09 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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// data_cnt_lim length changed to reduce number of warnings.
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//
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//
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// Revision 1.20 2004/03/28 20:27:02 igorm
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// Revision 1.20 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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// New release of the debug interface (3rd. release).
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| Line 250... |
Line 253... |
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reg [1:0] ptr;
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reg [1:0] ptr;
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reg [2:0] fifo_cnt;
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reg [2:0] fifo_cnt;
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wire fifo_full;
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wire fifo_full;
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wire fifo_empty;
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wire fifo_empty;
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//reg [7:0] mem [0:3];
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reg [7:0] mem [0:3];
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reg [7:0] mem0, mem1, mem2, mem3;
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reg [2:0] mem_ptr_dsff;
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reg [2:0] mem_ptr_dsff;
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reg wishbone_ce_csff;
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reg wishbone_ce_csff;
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reg mem_ptr_init;
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reg mem_ptr_init;
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reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
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reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
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wire curr_cmd_go;
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wire curr_cmd_go;
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| Line 316... |
Line 318... |
dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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end
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end
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else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
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else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
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begin
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begin
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case (acc_type) // synthesis parallel_case full_case
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if (acc_type == `DBG_WB_READ8)
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`DBG_WB_READ8 : begin
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begin
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if(byte & (~byte_q))
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if(byte & (~byte_q))
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begin
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begin
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case (ptr) // synthesis parallel_case
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case (ptr) // synthesis parallel_case
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2'b00 : dr[31:24] <= #1 input_data[31:24];
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2'b00 : dr[31:24] <= #1 input_data[31:24];
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2'b01 : dr[31:24] <= #1 input_data[23:16];
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2'b01 : dr[31:24] <= #1 input_data[23:16];
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| Line 334... |
Line 336... |
begin
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begin
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dr[31:24] <= #1 {dr[30:24], 1'b0};
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dr[31:24] <= #1 {dr[30:24], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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end
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end
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end
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end
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`DBG_WB_READ16: begin
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else if (acc_type == `DBG_WB_READ16)
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begin
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if(half & (~half_q))
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if(half & (~half_q))
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begin
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begin
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if (ptr[1])
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if (ptr[1])
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dr[31:16] <= #1 input_data[15:0];
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dr[31:16] <= #1 input_data[15:0];
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else
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else
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| Line 349... |
Line 352... |
begin
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begin
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dr[31:16] <= #1 {dr[30:16], 1'b0};
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dr[31:16] <= #1 {dr[30:16], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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end
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end
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end
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end
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`DBG_WB_READ32: begin
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else if (acc_type == `DBG_WB_READ32)
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begin
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if(long & (~long_q))
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if(long & (~long_q))
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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end
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end
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| Line 361... |
Line 365... |
begin
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begin
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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end
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end
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end
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end
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endcase
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end
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end
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else if (enable && (!addr_len_cnt_end))
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else if (enable && (!addr_len_cnt_end))
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begin
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begin
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dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
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dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
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end
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end
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| Line 608... |
Line 611... |
len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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else if(update_dr_i)
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else if(update_dr_i)
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len_var <= #1 len + 1'b1;
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len_var <= #1 len + 1'b1;
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else if (start_rd_tck)
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else if (start_rd_tck)
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begin
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begin
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case (acc_type) // synthesis parallel_case full_case
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case (acc_type) // synthesis parallel_case
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`DBG_WB_READ8 :
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`DBG_WB_READ8 :
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if (len_var > 'd1)
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if (len_var > 'd1)
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len_var <= #1 len_var - 1'd1;
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len_var <= #1 len_var - 1'd1;
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else
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else
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len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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| Line 624... |
Line 627... |
`DBG_WB_READ32:
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`DBG_WB_READ32:
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if (len_var > 'd4)
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if (len_var > 'd4)
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len_var <= #1 len_var - 3'd4;
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len_var <= #1 len_var - 3'd4;
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else
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else
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len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
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default: len_var <= #1 {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
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endcase
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endcase
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end
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end
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end
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end
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| Line 820... |
Line 824... |
begin
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begin
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if (rst_i)
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if (rst_i)
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wb_sel_dsff[3:0] <= #1 4'h0;
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wb_sel_dsff[3:0] <= #1 4'h0;
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else
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else
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begin
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begin
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case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case full_case
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case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case
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{2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8;
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{2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8;
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{2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC;
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{2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC;
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{2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF;
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{2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF;
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{2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4;
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{2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4;
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{2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2;
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{2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2;
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{2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3;
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{2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3;
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{2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1;
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{2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1;
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default: wb_sel_dsff[3:0] <= #1 4'hx;
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endcase
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endcase
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end
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end
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end
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end
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| Line 1016... |
Line 1021... |
mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
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mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
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end
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end
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end
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end
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/* Logic for latching data that is read from wishbone
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always @ (posedge wb_clk_i)
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begin
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if (wb_ack_i)
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begin
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case (wb_sel_dsff) // synthesis parallel_case full_case
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4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte
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4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte
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4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte
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4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte
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4'b1100 : // half
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begin
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mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
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mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
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end
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4'b0011 : // half
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begin
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mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
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mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
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end
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4'b1111 : // long
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begin
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mem[0] <= #1 wb_dat_i[31:24];
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mem[1] <= #1 wb_dat_i[23:16];
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mem[2] <= #1 wb_dat_i[15:08];
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mem[3] <= #1 wb_dat_i[07:00];
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end
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endcase
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end
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end
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*/
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|
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// Logic for latching data that is read from wishbone
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// Logic for latching data that is read from wishbone
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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begin
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begin
|
if (wb_ack_i)
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if (wb_ack_i)
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begin
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begin
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case (wb_sel_dsff) // synthesis parallel_case full_case
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case (wb_sel_dsff) // synthesis parallel_case
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4'b1000 : begin
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4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte
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case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte
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2'b00: mem0 <= #1 wb_dat_i[31:24];
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4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte
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2'b01: mem1 <= #1 wb_dat_i[31:24];
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4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte
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2'b10: mem2 <= #1 wb_dat_i[31:24];
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2'b11: mem3 <= #1 wb_dat_i[31:24];
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endcase
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end
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4'b0100 : begin
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case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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2'b00: mem0 <= #1 wb_dat_i[23:16];
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2'b01: mem1 <= #1 wb_dat_i[23:16];
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2'b10: mem2 <= #1 wb_dat_i[23:16];
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2'b11: mem3 <= #1 wb_dat_i[23:16];
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endcase
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end
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4'b0010 : begin
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case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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2'b00: mem0 <= #1 wb_dat_i[15:08];
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2'b01: mem1 <= #1 wb_dat_i[15:08];
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2'b10: mem2 <= #1 wb_dat_i[15:08];
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2'b11: mem3 <= #1 wb_dat_i[15:08];
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endcase
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end
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4'b0001 : begin
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case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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2'b00: mem0 <= #1 wb_dat_i[07:00];
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2'b01: mem1 <= #1 wb_dat_i[07:00];
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2'b10: mem2 <= #1 wb_dat_i[07:00];
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2'b11: mem3 <= #1 wb_dat_i[07:00];
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|
endcase
|
|
end
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|
|
|
4'b1100 : // half
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4'b1100 : // half
|
begin
|
begin
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
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2'b00: mem0 <= #1 wb_dat_i[31:24];
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mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
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2'b01: mem1 <= #1 wb_dat_i[31:24];
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|
2'b10: mem2 <= #1 wb_dat_i[31:24];
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|
2'b11: mem3 <= #1 wb_dat_i[31:24];
|
|
endcase
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|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
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|
2'b00: mem1 <= #1 wb_dat_i[23:16];
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2'b01: mem2 <= #1 wb_dat_i[23:16];
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|
2'b10: mem3 <= #1 wb_dat_i[23:16];
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|
2'b11: mem0 <= #1 wb_dat_i[23:16];
|
|
endcase
|
|
end
|
end
|
4'b0011 : // half
|
4'b0011 : // half
|
begin
|
begin
|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
|
2'b00: mem0 <= #1 wb_dat_i[15:08];
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mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
|
2'b01: mem1 <= #1 wb_dat_i[15:08];
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|
2'b10: mem2 <= #1 wb_dat_i[15:08];
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|
2'b11: mem3 <= #1 wb_dat_i[15:08];
|
|
endcase
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|
case (mem_ptr_dsff[1:0]) // synthesis parallel_case full_case
|
|
2'b00: mem1 <= #1 wb_dat_i[07:00];
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|
2'b01: mem2 <= #1 wb_dat_i[07:00];
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2'b10: mem3 <= #1 wb_dat_i[07:00];
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2'b11: mem0 <= #1 wb_dat_i[07:00];
|
|
endcase
|
|
end
|
end
|
4'b1111 : // long
|
4'b1111 : // long
|
begin
|
begin
|
mem0 <= #1 wb_dat_i[31:24];
|
mem[0] <= #1 wb_dat_i[31:24];
|
mem1 <= #1 wb_dat_i[23:16];
|
mem[1] <= #1 wb_dat_i[23:16];
|
mem2 <= #1 wb_dat_i[15:08];
|
mem[2] <= #1 wb_dat_i[15:08];
|
mem3 <= #1 wb_dat_i[07:00];
|
mem[3] <= #1 wb_dat_i[07:00];
|
|
end
|
|
default : // long
|
|
begin
|
|
mem[0] <= #1 8'hxx;
|
|
mem[1] <= #1 8'hxx;
|
|
mem[2] <= #1 8'hxx;
|
|
mem[3] <= #1 8'hxx;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
assign input_data = {mem0, mem1, mem2, mem3};
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
|
|
|
// Fifo counter and empty/full detection
|
// Fifo counter and empty/full detection
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
| Line 1143... |
Line 1074... |
fifo_cnt <= #1 3'h0;
|
fifo_cnt <= #1 3'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
fifo_cnt <= #1 3'h0;
|
fifo_cnt <= #1 3'h0;
|
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
|
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case full_case
|
case (acc_type) // synthesis parallel_case
|
`DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
|
`DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
|
`DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
|
`DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
|
`DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
|
`DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
|
|
default: fifo_cnt <= #1 3'bxxx;
|
endcase
|
endcase
|
end
|
end
|
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
|
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
|
begin
|
begin
|
case (acc_type) // synthesis parallel_case full_case
|
case (acc_type) // synthesis parallel_case
|
`DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
|
`DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
|
`DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
|
`DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
|
`DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
|
`DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
|
|
default: fifo_cnt <= #1 3'bxxx;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
