| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2004/01/06 17:15:19 mohor
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// temp3 version.
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//
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// Revision 1.4 2004/01/05 12:16:00 mohor
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// Revision 1.4 2004/01/05 12:16:00 mohor
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// tmp2 version.
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// tmp2 version.
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//
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//
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Tmp version.
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// Tmp version.
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| Line 153... |
Line 156... |
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reg [2:0] cmd, cmd_old;
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reg [2:0] cmd, cmd_old;
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reg [31:0] adr;
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reg [31:0] adr;
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reg [15:0] len;
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reg [15:0] len;
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reg start_tck;
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reg start_rd_tck;
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reg start_sync1;
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reg start_rd_sync1;
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reg start_wb;
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reg start_wb_rd;
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reg start_wb_q;
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reg start_wb_rd_q;
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reg start_wr_tck;
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reg start_wr_sync1;
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reg start_wb_wr;
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reg start_wb_wr_q;
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reg cmd_write;
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reg cmd_read;
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reg cmd_go;
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wire status_cnt_end;
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wire status_cnt_end;
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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//wire previous_cmd_read;
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wire previous_cmd_write;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); // igor !!! Add something so CRC is calculated when data is read from WB
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end)))
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if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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dr <= #1 {dr[49:0], tdi_i};
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dr <= #1 {dr[49:0], tdi_i};
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end
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end
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| Line 208... |
Line 223... |
begin
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begin
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if (trst_i)
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if (trst_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if (enable & cmd_cnt_end & (~data_cnt_end))
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// else if (enable & cmd_cnt_end & (~data_cnt_end)) // igor !!! add something that will count output data
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else if (enable & (~data_cnt_end) & cmd_go & ((cmd_cnt_end & previous_cmd_write | crc_cnt_end & cmd_read)))
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data_cnt <= #1 data_cnt + 1'b1;
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data_cnt <= #1 data_cnt + 1'b1;
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end
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end
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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assign byte = data_cnt[2:0] == 3'h0;
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assign byte = data_cnt[2:0] == 3'h0;
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assign half = data_cnt[3:0] == 4'h0;
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assign half = data_cnt[3:0] == 4'h0;
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assign long = data_cnt[4:0] == 5'h0;
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assign long = data_cnt[4:0] == 5'h0;
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| Line 231... |
Line 244... |
long_q <= #1 long;
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long_q <= #1 long;
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end
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end
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reg cmd_write;
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reg cmd_read;
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reg cmd_go;
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//wire previous_cmd_read;
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wire previous_cmd_write;
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//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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reg [2:0] cmd_new;
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wire dr_read;
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wire dr_write;
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always @ (posedge tck_i or posedge trst_i)
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wire dr_go;
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begin
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wire dr_status;
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if (trst_i)
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cmd_new <= #1 3'h0;
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assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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cmd_new <= #1 dr[2:0];
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assign dr_go = dr[2:0] == `WB_GO;
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end
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assign dr_status = dr[2:0] == `WB_STATUS;
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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cmd_read <= #1 1'b0;
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cmd_read <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_read <= #1 (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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cmd_read <= #1 dr_read;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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cmd_write <= #1 1'b0;
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cmd_write <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_write <= #1 (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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cmd_write <= #1 dr_write;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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cmd_go <= #1 1'b0;
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cmd_go <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_go <= #1 (dr[2:0] == `WB_GO);
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cmd_go <= #1 dr_go;
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end
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end
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| Line 286... |
Line 293... |
always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
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always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
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begin
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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begin
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begin
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// (current command is WB_STATUS or WB_GO)
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// (current command is WB_STATUS or WB_GO)
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if ( (dr[2:0] == `WB_STATUS) | (dr[2:0] == `WB_GO) )
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if (dr_status | dr_go)
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addr_len_cnt_limit = 6'd0;
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addr_len_cnt_limit = 6'd0;
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// (current command is WB_WRITEx or WB_READx)
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// (current command is WB_WRITEx or WB_READx)
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else
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else
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addr_len_cnt_limit = 6'd48;
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addr_len_cnt_limit = 6'd48;
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end
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end
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| Line 301... |
Line 308... |
always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
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always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
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begin
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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begin
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begin
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// (current command is WB_GO and previous command is WB_WRITEx)
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// (current command is WB_GO and previous command is WB_WRITEx)
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if ( (dr[2:0] == `WB_GO) & previous_cmd_write )
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if (dr_go & previous_cmd_write)
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data_cnt_limit = (len<<3);
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data_cnt_limit = (len<<3);
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else
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else
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data_cnt_limit = 19'h0;
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data_cnt_limit = 19'h0;
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end
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end
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end
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end
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`define WB_STATUS 3'h0
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`define WB_WRITE8 3'h1
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`define WB_WRITE16 3'h2
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`define WB_WRITE32 3'h3
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`define WB_GO 3'h4
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`define WB_READ8 3'h5
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`define WB_READ16 3'h6
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`define WB_READ32 3'h7
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 'h0;
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| Line 339... |
Line 333... |
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
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//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign data_cnt_end = data_cnt == data_cnt_limit;
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assign data_cnt_end = (data_cnt == data_cnt_limit);
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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crc_cnt_end_q <= #1 crc_cnt_end;
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crc_cnt_end_q <= #1 crc_cnt_end;
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cmd_cnt_end_q <= #1 cmd_cnt_end;
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cmd_cnt_end_q <= #1 cmd_cnt_end;
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| Line 416... |
Line 410... |
tdo_o = 1'b0;
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tdo_o = 1'b0;
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TDO_WISHBONE = "zero while CRC is shifted in";
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TDO_WISHBONE = "zero while CRC is shifted in";
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end
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end
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end
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end
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assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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| Line 443... |
Line 436... |
else
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else
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set_addr <= #1 1'b0;
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set_addr <= #1 1'b0;
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end
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end
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// Start wishbone read cycle
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always @ (posedge tck_i)
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begin
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if (set_addr & cmd_read)
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start_rd_tck <= #1 1'b1;
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else
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start_rd_tck <= #1 1'b0;
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end
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// Start wishbone write cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_go & previous_cmd_write)
|
if (cmd_go & previous_cmd_write)
|
begin
|
begin
|
case (cmd) // synthesis parallel_case full_case
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case (cmd) // synthesis parallel_case full_case
|
`WB_WRITE8 : begin
|
`WB_WRITE8 : begin
|
if (byte & (~byte_q))
|
if (byte & (~byte_q))
|
begin
|
begin
|
start_tck <= #1 1'b1;
|
start_wr_tck <= #1 1'b1;
|
wb_dat_o <= #1 {4{dr[7:0]}};
|
wb_dat_o <= #1 {4{dr[7:0]}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
start_tck <= #1 1'b0;
|
start_wr_tck <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`WB_WRITE16 : begin
|
`WB_WRITE16 : begin
|
if (half & (~half_q))
|
if (half & (~half_q))
|
begin
|
begin
|
start_tck <= #1 1'b1;
|
start_wr_tck <= #1 1'b1;
|
wb_dat_o <= #1 {2{dr[15:0]}};
|
wb_dat_o <= #1 {2{dr[15:0]}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
start_tck <= #1 1'b0;
|
start_wr_tck <= #1 1'b0;
|
end
|
end
|
end
|
end
|
`WB_WRITE32 : begin
|
`WB_WRITE32 : begin
|
if (long & (~long_q))
|
if (long & (~long_q))
|
begin
|
begin
|
start_tck <= #1 1'b1;
|
start_wr_tck <= #1 1'b1;
|
wb_dat_o <= #1 dr[31:0];
|
wb_dat_o <= #1 dr[31:0];
|
end
|
end
|
else
|
else
|
begin
|
begin
|
start_tck <= #1 1'b0;
|
start_wr_tck <= #1 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
start_tck <= #1 1'b0;
|
start_wr_tck <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
start_sync1 <= #1 start_tck;
|
start_rd_sync1 <= #1 start_rd_tck;
|
start_wb <= #1 start_sync1;
|
start_wb_rd <= #1 start_rd_sync1;
|
start_wb_q <= #1 start_wb;
|
start_wb_rd_q <= #1 start_wb_rd;
|
|
|
|
start_wr_sync1 <= #1 start_wr_tck;
|
|
start_wb_wr <= #1 start_wr_sync1;
|
|
start_wb_wr_q <= #1 start_wb_wr;
|
|
|
set_addr_sync <= #1 set_addr;
|
set_addr_sync <= #1 set_addr;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb_q <= #1 set_addr_wb;
|
set_addr_wb_q <= #1 set_addr_wb;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
else if (start_wb & (~start_wb_q))
|
else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
|
wb_cyc_o <= #1 1'b1;
|
wb_cyc_o <= #1 1'b1;
|
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
end
|
end
|
|
|
| Line 517... |
Line 527... |
begin
|
begin
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
wb_adr_o <= #1 adr;
|
wb_adr_o <= #1 adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if ((cmd_new == `WB_WRITE8) | (cmd == `WB_READ8))
|
if ((cmd == `WB_WRITE8) | (cmd_old == `WB_READ8))
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
else if ((cmd_new == `WB_WRITE16) | (cmd == `WB_READ16))
|
else if ((cmd == `WB_WRITE16) | (cmd_old == `WB_READ16))
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
else
|
else
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
end
|
end
|
end
|
end
|
|
|
|
`define WB_STATUS 3'h0 // igor !!! Delete this lines
|
|
`define WB_WRITE8 3'h1 // igor !!! Delete this lines
|
|
`define WB_WRITE16 3'h2 // igor !!! Delete this lines
|
|
`define WB_WRITE32 3'h3 // igor !!! Delete this lines
|
|
`define WB_GO 3'h4 // igor !!! Delete this lines
|
|
`define WB_READ8 3'h5 // igor !!! Delete this lines
|
|
`define WB_READ16 3'h6 // igor !!! Delete this lines
|
|
`define WB_READ32 3'h7 // igor !!! Delete this lines
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// adr byte | short | long
|
// adr byte | short | long
|
// 0 1000 1100 1111
|
// 0 1000 1100 1111
|
// 1 0100 err err
|
// 1 0100 err err
|
// 2 0010 0011 err
|
// 2 0010 0011 err
|
| Line 557... |
Line 581... |
/*
|
/*
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_o[31:0] <= #1 32'h0;
|
wb_dat_o[31:0] <= #1 32'h0;
|
else if (start_wb & (~start_wb_q))
|
else if (start_wb_wr & (~start_wb_wr_q))
|
begin
|
begin
|
if (cmd[1:0] == 2'd1) // 8-bit access
|
if (cmd[1:0] == 2'd1) // 8-bit access
|
wb_dat_o[31:0] <= #1 {4{8'h0}};
|
wb_dat_o[31:0] <= #1 {4{8'h0}};
|
else if (cmd[1:0] == 2'd2) // 16-bit access
|
else if (cmd[1:0] == 2'd2) // 16-bit access
|
wb_dat_o[31:0] <= #1 {2{16'h0}};
|
wb_dat_o[31:0] <= #1 {2{16'h0}};
|
| Line 684... |
Line 708... |
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
else if(start_wb & (~start_wb_q) & wb_cyc_o)
|
else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
|
wb_overrun <= #1 1'b1;
|
wb_overrun <= #1 1'b1;
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
end
|
end
|
|
|
