| Line 1... |
Line 1... |
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// igor !!! cmd_old_read poskusi dati ven
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_wb.v ////
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//// dbg_wb.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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| Line 41... |
Line 45... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2004/01/09 12:48:44 mohor
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// tmp version.
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//
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// Revision 1.7 2004/01/08 17:53:36 mohor
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// Revision 1.7 2004/01/08 17:53:36 mohor
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// tmp version.
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// tmp version.
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//
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//
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// Revision 1.6 2004/01/07 11:58:56 mohor
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// Revision 1.6 2004/01/07 11:58:56 mohor
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// temp4 version.
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// temp4 version.
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| Line 173... |
Line 180... |
reg start_wr_tck;
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reg start_wr_tck;
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reg start_wr_sync1;
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reg start_wr_sync1;
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reg start_wb_wr;
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reg start_wb_wr;
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reg start_wb_wr_q;
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reg start_wb_wr_q;
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wire dr_read;
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wire dr_write;
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wire dr_go;
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reg dr_write_latched;
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reg dr_write_latched;
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reg dr_read_latched;
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reg dr_read_latched;
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reg dr_go_latched;
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reg dr_go_latched;
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wire status_cnt_end;
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wire status_cnt_end;
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| Line 184... |
Line 195... |
wire byte, half, long;
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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reg byte_q, half_q, long_q;
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reg cmd_read;
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reg cmd_read;
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reg cmd_write;
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reg cmd_write;
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reg cmd_go;
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reg cmd_go;
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reg cmd_old_read;
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//reg cmd_old_read;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
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reg [`STATUS_LEN -1:0] status;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
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reg busy_wb;
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reg busy_tck;
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reg wb_end;
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reg wb_end_rst;
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reg wb_end_rst_sync;
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reg wb_end_sync;
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reg wb_end_tck;
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reg busy_sync;
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reg [799:0] TDO_WISHBONE;
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reg [399:0] latching_data;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg read_cycle;
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reg [2:0] read_type;
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wire [31:0] input_data;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
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| Line 200... |
Line 231... |
//begin
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//begin
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// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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// dr <= #1 {dr[49:0], tdi_i};
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// dr <= #1 {dr[49:0], tdi_i};
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//end
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//end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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/* if (cmd_old_read & cmd_go)
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// if (cmd_old_read & cmd_go)
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begin
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if (read_cycle & cmd_go)
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case (cmd_old) // synthesis parallel_case full_case
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begin
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`WB_READ8 : begin
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// case (cmd_old) // synthesis parallel_case full_case
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if(byte & (~byte_q))
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case (read_type) // synthesis parallel_case full_case
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dr[31:24] <= #1 input_data[];
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`WB_READ8 : begin
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else
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if(byte & (~byte_q))
|
dr <= #1 dr<<1;
|
begin
|
end
|
dr[31:24] <= #1 8'h08; // input_data[];
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`WB_READ16: begin
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latching_data = "8 bit latched";
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if(half & (~half_q))
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end
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start_rd_tck <= #1 1'b1;
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else
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else
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begin
|
start_rd_tck <= #1 1'b0;
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
end
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latching_data = "8 bit shifted";
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`WB_READ32: begin
|
end
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if(long & (~long_q))
|
end
|
start_rd_tck <= #1 1'b1;
|
`WB_READ16: begin
|
else
|
if(half & (~half_q))
|
start_rd_tck <= #1 1'b0;
|
begin
|
end
|
dr[31:16] <= #1 16'h1616;
|
endcase
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latching_data = "16 bit latched";
|
end
|
end
|
else*/ if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
else
|
|
begin
|
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
|
latching_data = "16 bit shifted";
|
|
end
|
|
end
|
|
`WB_READ32: begin
|
|
if(long & (~long_q))
|
|
begin
|
|
dr[31:0] <= #1 32'h32323232;
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|
latching_data = "32 bit latched";
|
|
end
|
|
else
|
|
begin
|
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
|
latching_data = "32 bit shifted";
|
|
end
|
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end
|
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endcase
|
|
end
|
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else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
|
begin
|
dr <= #1 {dr[49:0], tdi_i};
|
dr <= #1 {dr[49:0], tdi_i};
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|
latching_data = "tdi shifted in";
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|
end
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end
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end
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|
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|
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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| Line 278... |
Line 331... |
assign long = data_cnt[4:0] == 5'h0;
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assign long = data_cnt[4:0] == 5'h0;
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
|
begin
|
|
// if (crc_cnt == 6'd31) // Reset to zero after crc to load first data byte. igor !!! This is probably not necessary
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// begin
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// byte_q <= #1 1'b0;
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// half_q <= #1 1'b0;
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// long_q <= #1 1'b0;
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|
// end
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// else
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|
// begin
|
byte_q <= #1 byte;
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byte_q <= #1 byte;
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half_q <= #1 half;
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half_q <= #1 half;
|
long_q <= #1 long;
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long_q <= #1 long;
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|
// end
|
end
|
end
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|
|
//assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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//assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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//assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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//assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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//assign cmd_go = cmd == `WB_GO;
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//assign cmd_go = cmd == `WB_GO;
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//assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
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//assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
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wire dr_read;
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wire dr_write;
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wire dr_go;
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assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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assign dr_go = dr[2:0] == `WB_GO;
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assign dr_go = dr[2:0] == `WB_GO;
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| Line 334... |
Line 392... |
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (cmd_cnt == 2'h2)
|
if (update_dr_i)
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begin
|
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if (dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) // current command is WB_GO and previous command is WB_WRITEx)
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data_cnt_limit = (len<<3);
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else
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data_cnt_limit = 19'h0;
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end
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else if (crc_cnt == 6'd31)
|
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begin
|
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if (dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
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data_cnt_limit = (len<<3);
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else
|
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data_cnt_limit = 19'h0;
|
data_cnt_limit = 19'h0;
|
end
|
else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
|
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((crc_cnt == 6'd31) & dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
|
|
)
|
|
data_cnt_limit = {len, 3'b000};
|
end
|
end
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|
|
|
|
assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
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assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
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|
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| Line 384... |
Line 434... |
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
status_cnt1 <= #1 1'b0;
|
status_cnt1 <= #1 1'b0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
status_cnt1 <= #1 1'b0;
|
status_cnt1 <= #1 1'b0;
|
else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
|
// else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
|
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle |
|
crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
|
crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
|
)
|
)
|
status_cnt1 <= #1 1'b1;
|
status_cnt1 <= #1 1'b1;
|
end
|
end
|
|
|
| Line 414... |
Line 465... |
status_cnt4 <= #1 status_cnt3;
|
status_cnt4 <= #1 status_cnt3;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
assign status_cnt_end = status_cnt4;
|
assign status_cnt_end = status_cnt4;
|
reg [`STATUS_LEN -1:0] status;
|
|
|
|
reg wb_error, wb_error_sync, wb_error_tck;
|
|
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
|
|
|
|
reg busy_wb;
|
|
reg busy_tck;
|
|
reg wb_end;
|
|
reg wb_end_rst;
|
|
reg wb_end_rst_sync;
|
|
reg wb_end_sync;
|
|
reg wb_end_tck;
|
|
reg busy_sync;
|
|
reg [799:0] TDO_WISHBONE;
|
|
|
|
|
|
|
|
|
reg [199:0] status_text;
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
|
begin
|
status <= #1 'h0;
|
status <= #1 'h0;
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~dr_read_latched))
|
status_text <= #1 "reset";
|
|
end
|
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
|
begin
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
else if (data_cnt_end & (~data_cnt_end_q) & dr_read_latched)
|
status_text <= #1 "!!!READ";
|
|
end
|
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
|
begin
|
status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
|
status_text <= #1 "READ";
|
|
end
|
else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
|
begin
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
|
status_text <= #1 "shift";
|
|
end
|
end
|
end
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
| Line 466... |
Line 511... |
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
TDO_WISHBONE = "crc_match_i";
|
TDO_WISHBONE = "crc_match_i";
|
end
|
end
|
else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated
|
// else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated
|
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) // cmd is already updated
|
begin
|
begin
|
tdo_o = crc_match_reg;
|
tdo_o = crc_match_reg;
|
TDO_WISHBONE = "crc_match_reg";
|
TDO_WISHBONE = "crc_match_reg";
|
end
|
end
|
else if (crc_cnt_end & (~(dr_go_latched & cmd_old_read)) | data_cnt_end & dr_go_latched & cmd_old_read) // cmd is already updated
|
// else if (crc_cnt_end & (~read_cycle) | data_cnt_end & read_cycle) // cmd is already updated
|
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
TDO_WISHBONE = "status";
|
TDO_WISHBONE = "status";
|
end
|
end
|
else
|
else
|
| Line 484... |
Line 531... |
TDO_WISHBONE = "zero while CRC is shifted in";
|
TDO_WISHBONE = "zero while CRC is shifted in";
|
end
|
end
|
end
|
end
|
|
|
|
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
crc_match_reg <= #1 crc_match_i;
|
crc_match_reg <= #1 crc_match_i;
|
| Line 521... |
Line 567... |
cmd <= #1 'h0;
|
cmd <= #1 'h0;
|
cmd_old <= #1 'h0;
|
cmd_old <= #1 'h0;
|
cmd_read <= #1 1'b0;
|
cmd_read <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
cmd_old_read <= #1 1'b0;
|
// cmd_old_read <= #1 1'b0;
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
cmd <= #1 dr_cmd_latched;
|
cmd <= #1 dr_cmd_latched;
|
cmd_old <= #1 cmd;
|
cmd_old <= #1 cmd;
|
cmd_read <= #1 dr_read_latched;
|
cmd_read <= #1 dr_read_latched;
|
cmd_write <= #1 dr_write_latched;
|
cmd_write <= #1 dr_write_latched;
|
cmd_go <= #1 dr_go_latched;
|
cmd_go <= #1 dr_go_latched;
|
cmd_old_read <= #1 cmd_read;
|
// cmd_old_read <= #1 cmd_read;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
| Line 550... |
Line 596... |
end
|
end
|
else
|
else
|
set_addr <= #1 1'b0;
|
set_addr <= #1 1'b0;
|
end
|
end
|
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (set_addr & dr_read_latched)
|
// if (set_addr & dr_read_latched)
|
if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
// else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
|
else if (read_cycle)
|
begin
|
begin
|
case (cmd_old) // synthesis parallel_case full_case
|
case (read_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else
|
else
|
start_rd_tck <= #1 1'b0;
|
start_rd_tck <= #1 1'b0;
|
| Line 585... |
Line 631... |
else
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else
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start_rd_tck <= #1 1'b0;
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start_rd_tck <= #1 1'b0;
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end
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end
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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read_cycle <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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read_cycle <= #1 1'b1;
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end
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always @ (posedge tck_i)
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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read_type <= #1 cmd;
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end
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// Start wishbone write cycle
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// Start wishbone write cycle
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (dr_go_latched & cmd_write)
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if (dr_go_latched & cmd_write)
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| Line 666... |
Line 730... |
begin
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begin
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if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
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if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
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wb_adr_o <= #1 adr;
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wb_adr_o <= #1 adr;
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else if (wb_ack_i)
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else if (wb_ack_i)
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begin
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begin
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if ((cmd == `WB_WRITE8) | (cmd_old == `WB_READ8))
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if ((cmd == `WB_WRITE8) | (read_type == `WB_READ8))
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wb_adr_o <= #1 wb_adr_o + 1'd1;
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wb_adr_o <= #1 wb_adr_o + 1'd1;
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else if ((cmd == `WB_WRITE16) | (cmd_old == `WB_READ16))
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else if ((cmd == `WB_WRITE16) | (read_type == `WB_READ16))
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wb_adr_o <= #1 wb_adr_o + 2'd2;
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wb_adr_o <= #1 wb_adr_o + 2'd2;
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else
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else
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wb_adr_o <= #1 wb_adr_o + 3'd4;
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wb_adr_o <= #1 wb_adr_o + 3'd4;
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end
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end
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end
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end
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// adr byte | short | long
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// adr byte | short | long
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// 0 1000 1100 1111
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// 0 1000 1100 1111
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// 1 0100 err err
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// 1 0100 err err
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// 2 0010 0011 err
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// 2 0010 0011 err
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// 3 0001 err err
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// 3 0001 err err
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| Line 700... |
Line 761... |
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
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wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
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end
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end
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else // read
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else // read
|
begin
|
begin
|
wb_sel_o[0] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
wb_sel_o[0] <= #1 (read_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (read_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
(cmd_old[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
(read_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1] ^ cmd_old[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (read_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (read_type[1] ^ read_type[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[2] <= #1 (cmd_old[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[2] <= #1 (read_type[1]) & (wb_adr_o[1:0] == 2'b00) | (read_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
end
|
end
|
end
|
end
|
|
|
|
|
| Line 715... |
Line 776... |
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
|
|
reg [31:0] input_data;
|
|
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if(wb_ack_i)
|
|
input_data <= #1 wb_dat_i;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
| Line 834... |
Line 886... |
status_reset_en <= #1 1'b1;
|
status_reset_en <= #1 1'b1;
|
else
|
else
|
status_reset_en <= #1 1'b0;
|
status_reset_en <= #1 1'b0;
|
end
|
end
|
|
|
|
/*
|
|
to gre ven
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
|
wb_adr_o <= #1 adr;
|
|
else if (wb_ack_i)
|
|
begin
|
|
if (read_type == `WB_READ8)
|
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
|
else if (read_type == `WB_READ16)
|
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
|
else
|
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
|
end
|
|
end
|
|
*/
|
|
reg [7:0] mem [0:3];
|
|
reg [2:0] mem_ptr;
|
|
reg wishbone_ce_sync;
|
|
reg wishbone_ce_rst;
|
|
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
wishbone_ce_sync <= #1 wishbone_ce_i;
|
|
wishbone_ce_rst <= #1 ~wishbone_ce_sync;
|
|
end
|
|
|
|
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if(wishbone_ce_rst)
|
|
mem_ptr <= #1 'h0;
|
|
else if (wb_ack_i)
|
|
begin
|
|
if (read_type == `WB_READ8)
|
|
mem_ptr <= #1 mem_ptr + 1'd1;
|
|
else if (read_type == `WB_READ16)
|
|
mem_ptr <= #1 mem_ptr + 2'd2;
|
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if (wb_ack_i)
|
|
begin
|
|
case (wb_sel_o) // synthesis parallel_case full_case
|
|
4'b1000 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; // byte
|
|
4'b0100 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16]; // byte
|
|
4'b0010 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; // byte
|
|
4'b0001 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:01]; // byte
|
|
|
|
4'b1100 : // half
|
|
begin
|
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];
|
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
|
|
end
|
|
4'b0011 : // half
|
|
begin
|
|
mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];
|
|
mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:01];
|
|
end
|
|
4'b1111 : // long
|
|
begin
|
|
mem[0] <= #1 wb_dat_i[31:24];
|
|
mem[1] <= #1 wb_dat_i[23:16];
|
|
mem[2] <= #1 wb_dat_i[15:08];
|
|
mem[3] <= #1 wb_dat_i[07:01];
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
|
|
|
|
|
|
|
|
|
