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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_wb_defines.v] - Diff between revs 139 and 141

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Rev 139 Rev 141
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2004/03/28 20:27:02  igorm
 
// New release of the debug interface (3rd. release).
 
//
// Revision 1.5  2004/03/22 16:35:46  igorm
// Revision 1.5  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
// Temp version before changing dbg interface.
//
//
// Revision 1.4  2004/01/16 14:51:33  mohor
// Revision 1.4  2004/01/16 14:51:33  mohor
// cpu registers added.
// cpu registers added.
Line 85... Line 88...
`define DBG_WB_STATUS_LEN       3'd4
`define DBG_WB_STATUS_LEN       3'd4
`define DBG_WB_STATUS_CNT_WIDTH 3
`define DBG_WB_STATUS_CNT_WIDTH 3
 
 
// Defining length of the data
// Defining length of the data
`define DBG_WB_DATA_CNT_WIDTH   (`DBG_WB_LEN_LEN + 3)
`define DBG_WB_DATA_CNT_WIDTH   (`DBG_WB_LEN_LEN + 3)
 
`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
 
 
//Defining commands
//Defining commands
`define DBG_WB_GO               4'h0
`define DBG_WB_GO               4'h0
`define DBG_WB_RD_COMM          4'h1
`define DBG_WB_RD_COMM          4'h1
`define DBG_WB_WR_COMM          4'h2
`define DBG_WB_WR_COMM          4'h2

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