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# A Double-Clocked FFT Core Generator
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# A Generic Piplined FFT Core Generator
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The Double Clocked FFT project contains all of the software necessary to
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This generic pipelined FFT project contains all of the software necessary to
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create the IP to generate an arbitrary sized FFT that will clock two samples
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create the IP to generate an arbitrary sized FFT. The FFT has been modified
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in at each clock cycle, and after some pipeline delay it will clock two
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for operation in one of the following modes:
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samples out at every clock cycle.
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- Two samples in per clock and, after some delay, two samples out per clock.
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This uses 6 multiplies per FFT stage in the butterflies. This was the purpose
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of the original `dblclkfft`. (Why double clock? I don't know. Double-sample
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FFT might've been a better name.)
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- One sample in per clock, with the `i_ce` line being high for every incoming
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sample--up to one sample per clock. There's also options to run with at
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least one clock between samples, or even two clocks between samples (or more).
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This mode uses 3, 2, or 1 multiplies per FFT stage respectively.
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- Eventually, I want to support a real FFT mode which will accept real samples
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input, and alternately produce real and imaginary samples output--or the
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converse for the inverse FFT.
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The FFT generated by this approach is very configurable. By simple adjustment
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The FFT generated by this project is very configurable. By simple adjustment
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of a command line parameter, the FFT may be made to be a forward FFT or an
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of a command line parameter, the FFT created will either be a forward FFT or an
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inverse FFT. The number of bits processed, kept, and maintained by this
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inverse FFT. The number of bits processed, kept, and maintained by this
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FFT are also configurable. Even the number of bits used for the twiddle
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FFT are also configurable. Even the number of bits used for the twiddle
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factors, or whether or not to bit reverse the outputs, are all configurable
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factors, or whether or not to bit reverse the outputs, are all configurable
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parts to this FFT core.
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parts to this FFT core.
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These features make the Double Clocked FFT very different and unique among the
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These features make this open source pipelined FFT module very different
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other open HDL cores you may fine.
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and unique among the other open HDL cores you may find.
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For those who wish to get started right away, please download the package,
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For those who wish to get started right away, please download the package,
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change into the ``sw`` directory and run ``make``. There is no need to
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change into the ``sw`` directory and run ``make``. There is no need to
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run a configure script, ``fftgen`` is completely portable C++. Then, once
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run a configure script, ``fftgen`` is completely portable C++. Then, once
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built, go ahead and run ``fftgen`` without any arguments. This will cause
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built, go ahead and run ``fftgen`` without any arguments. This will cause
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``fftgen`` to print a usage statement to the screen. Review the usage
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``fftgen`` to print a usage statement to the screen. Review the usage
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statement, and run ``fftgen`` a second time with the arguments you need.
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statement, and run ``fftgen`` a second time with the arguments you need.
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Alternatively, you _could_ read the specification.
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# Current State
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## Genesis
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This particular version of the FFT core now passes all my tests. It has
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This FFT comes from my attempts to design and implement a signal processing
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yet to meet hardware to be finally verified.
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algorithm inside a generic FPGA, but only on a limited budget. As such,
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I don't yet have the FPGA board I wish to place this algorithm onto, neither
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do I have any expensive modeling or simulation capabilities. I'm using
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Verilator for my modeling and simulation needs. This makes
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using a vendor supplied IP core, such as an FFT, difficult if not impossible
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to use.
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My problem was made worse when I learned that the published maximum clock
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speed for a device wasn't necessarily the maximum clock speed that I could
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achieve. My design needed to process the incoming signal at 500 MHz to be
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commercially viable. 500 MHz is not necessarily a clock speed
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that can be easily achieved. 250 MHz, on the other hand, is much more within
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the realm of possibility. Achieving a 500 MHz performance with a 250 MHz
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clock, however, requires an FFT that accepts two samples per clock.
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This, then, was and is the genesis of this project.
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- The [FFT test bench](bench/cpp/fft_tb.cpp) doesn't yet have a threshold that
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adjusts with input parameters to determine success or failure (yet).
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- I haven't started on the real-only version of this FFT.
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While my previously stated goal ws to continue working with this core until it
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has a real-FFT capability before releasing it back into the master branch,
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I'm actually so excited that I got it to this point that I'm going to move
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it from dev to master earlier, and come back to get the real only version.
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# Commercial Applications
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# Commercial Applications
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Should you find the GPLv3 license insufficient for your needs, other licenses
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Should you find the GPLv3 license insufficient for your needs, other licenses
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can be purchased from Gisselquist Technology, LLC.
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can be purchased from Gisselquist Technology, LLC.
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Likewise, please contact us should you wish to fund the further development
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Likewise, please contact us should you wish to fund the further development
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of this core.
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of this core.
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Watch this space if you are interested in a release under another license.
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I'm thinking about relicensing this with a more permissive license.
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