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#include <stdio.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdint.h>
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#include "Vqtrstage.h"
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#include "Vqtrstage.h"
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#include "verilated.h"
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#include "verilated.h"
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#include "twoc.h"
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#define IWIDTH 16
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#define IWIDTH 16
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#define OWIDTH (IWIDTH+1)
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#define OWIDTH (IWIDTH+1)
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#define LGWIDTH 8
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#define LGWIDTH 8
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void tick(Vqtrstage *qstage) {
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#define ASIZ 32
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qstage->i_clk = 0;
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#define AMSK (ASIZ-1)
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qstage->eval();
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qstage->i_clk = 1;
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class QTRTEST_TB {
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qstage->eval();
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public:
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Vqtrstage *m_qstage;
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unsigned long m_data[ASIZ];
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int m_addr, m_offset;
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bool m_syncd;
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QTRTEST_TB(void) {
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m_qstage = new Vqtrstage;
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m_addr = 0; m_offset = 6; m_syncd = false;
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}
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}
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void reset(Vqtrstage *qstage) {
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void tick(void) {
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qstage->i_ce = 0;
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m_qstage->i_clk = 0;
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qstage->i_rst = 1;
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m_qstage->eval();
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tick(qstage);
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m_qstage->i_clk = 1;
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qstage->i_ce = 0;
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m_qstage->eval();
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qstage->i_rst = 0;
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tick(qstage);
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m_qstage->i_sync = 0;
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}
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}
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int main(int argc, char **argv, char **envp) {
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void reset(void) {
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Verilated::commandArgs(argc, argv);
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m_qstage->i_ce = 0;
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Vqtrstage *qstage = new Vqtrstage;
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m_qstage->i_rst = 1;
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int16_t ir0, ii0, lstr, lsti;
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tick();
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int32_t sumr, sumi, difr, difi;
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m_qstage->i_ce = 0;
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int32_t smr, smi, dfr, dfi;
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m_qstage->i_rst = 0;
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int rnd = 0; // Can only be set to true if OWIDTH=IWIDTH
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tick();
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if ((OWIDTH<IWIDTH+1)&&(rnd!=0)) {
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m_addr = 0; m_offset = 6; m_syncd = false;
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fprintf(stderr, "ERR: Rounding can only be applied when\n");
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fprintf(stderr, "\tthe output width is less than or equal\n");
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fprintf(stderr, "\tto the input width. Turn rounding off\n");
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fprintf(stderr, "\trebuild, and try again.\n");
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assert(0 == rnd);
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}
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}
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reset(qstage);
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void check_results(void) {
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int ir0, ii0, ir1, ii1, ir2, ii2;
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int sumr, sumi, difr, difi, or0, oi0;
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bool fail = false;
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for(int k=0; k<1060; k++) {
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if ((!m_syncd)&&(m_qstage->o_sync)) {
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int32_t or0, oi0, or1, oi1;
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m_syncd = true;
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m_offset = m_addr;
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}
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qstage->i_ce = 1;
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if (!m_syncd)
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qstage->i_sync = ((k&0x0ff)==0);
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return;
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// Let's pick some random values, ...
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ir0 = rand(); if (ir0&4) ir0 = -ir0;
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ir0 = sbits(m_data[(m_addr-m_offset-1)&AMSK]>>IWIDTH, IWIDTH);
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ii0 = rand(); if (ii0&2) ii0 = -ii0;
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ii0 = sbits(m_data[(m_addr-m_offset-1)&AMSK], IWIDTH);
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ir1 = sbits(m_data[(m_addr-m_offset )&AMSK]>>IWIDTH, IWIDTH);
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ii1 = sbits(m_data[(m_addr-m_offset )&AMSK], IWIDTH);
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ir2 = sbits(m_data[(m_addr-m_offset+1)&AMSK]>>IWIDTH, IWIDTH);
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ii2 = sbits(m_data[(m_addr-m_offset+1)&AMSK], IWIDTH);
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sumr = ir1 + ir2;
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sumi = ii1 + ii2;
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difr = ir0 - ir1;
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difi = ii0 - ii1;
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or0 = sbits(m_qstage->o_data >> OWIDTH, OWIDTH);
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oi0 = sbits(m_qstage->o_data, OWIDTH);
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qstage->i_data = ((ir0&0x0ffff) << 16) | (ii0 & 0x0ffff);
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if (0==((m_addr-m_offset)&1)) {
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tick(qstage);
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if (or0 != sumr) {
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printf("FAIL 1: or0 != sumr (%x(exp) != %x(sut))\n", sumr, or0); fail = true;}
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if (oi0 != sumi) {
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printf("FAIL 2: oi0 != sumi (%x(exp) != %x(sut))\n", sumi, oi0); fail = true;}
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} else if (1==((m_addr-m_offset)&1)) {
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if (or0 != difr) {
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printf("FAIL 3: or0 != difr (%x(exp) != %x(sut))\n", difr, or0); fail = true;}
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if (oi0 != difi) {
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printf("FAIL 4: oi0 != difi (%x(exp) != %x(sut))\n", difi, oi0); fail = true;}
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}
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printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\n",
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if (m_qstage->o_sync != ((((m_addr-m_offset)&127) == 0)?1:0)) {
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k, qstage->i_sync, qstage->i_data,
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printf("BAD O-SYNC, m_addr = %d, m_offset = %d\n", m_addr, m_offset); fail = true;
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qstage->o_data, qstage->o_sync);
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}
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or0 = (qstage->o_data >> 17) & 0x01ffff;
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if (fail)
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oi0 = qstage->o_data & 0x01ffff;
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exit(-1);
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if (or0 & 0x010000) or0 |= (-1<<16);
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}
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if (oi0 & 0x010000) oi0 |= (-1<<16);
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if (k>3) {
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void sync(void) {
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/*
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m_qstage->i_sync = 1;
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printf("\tOR0 = %6x, OI0 = %6x, SUM = %6x + %6x, DIF = %6x + %6x\n",
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m_addr = 0;
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or0, oi0, sumr, sumi, difr, difi);
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*/
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if (0==(k&1)) {
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if (or0 != sumr) {fprintf(stderr, "FAIL 1\n"); exit(-1);}
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if (oi0 != sumi) {fprintf(stderr, "FAIL 2\n"); exit(-1);}
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} else if (1==(k&1)) {
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if (or0 != difr) {fprintf(stderr, "FAIL 3\n"); exit(-1);}
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if (oi0 != difi) {fprintf(stderr, "FAIL 4\n"); exit(-1);}
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}
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}
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void test(unsigned int data) {
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int isync = m_qstage->i_sync;
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m_qstage->i_ce = 1;
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m_qstage->i_data = data;
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// m_qstage->i_sync = (((m_addr&127)==2)?1:0);
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m_data[ (m_addr++)&AMSK] = data;
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tick();
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printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\t%5x,%5x,%5x,%5x\t%x %4x %8x %d\n",
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(m_addr-m_offset), isync, m_qstage->i_data,
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m_qstage->o_data, m_qstage->o_sync,
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m_qstage->v__DOT__sum_r,
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m_qstage->v__DOT__sum_i,
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m_qstage->v__DOT__diff_r,
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m_qstage->v__DOT__diff_i,
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m_qstage->v__DOT__pipeline,
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m_qstage->v__DOT__iaddr,
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m_qstage->v__DOT__imem,
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m_qstage->v__DOT__wait_for_sync);
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check_results();
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}
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}
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if (((4==(k&0x07f))?1:0) != qstage->o_sync) { fprintf(stderr, "BAD O-SYNC\n"); exit(-1); }
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void test(int ir0, int ii0) {
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unsigned int data;
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if (1 == (k&1)) {
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data = (((ir0&((1<<IWIDTH)-1)) << IWIDTH) | (ii0 & ((1<<IWIDTH)-1)));
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sumr = smr; sumi = smi; difr=dfr, difi= dfi;
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// printf("%d,%d -> %8x\n", ir0, ii0, data);
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test(data);
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}
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smr = lstr + ir0 + rnd;
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void random_test(void) {
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smi = lsti + ii0 + rnd;
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int ir0, ii0;
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dfr = lstr - ir0 + rnd;
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// Let's pick some random values
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dfi = lsti - ii0 + rnd;
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ir0 = rand(); if (ir0&4) ir0 = -ir0;
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ii0 = rand(); if (ii0&2) ii0 = -ii0;
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test(ir0, ii0);
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}
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}
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};
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int main(int argc, char **argv, char **envp) {
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Verilated::commandArgs(argc, argv);
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QTRTEST_TB *tb = new QTRTEST_TB;
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int16_t ir0, ii0, ir1, ii1, ir2, ii2;
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int32_t sumr, sumi, difr, difi;
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lstr = ir0;
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tb->reset();
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lsti = ii0;
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tb->test( 16, 0);
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tb->test( 16, 0);
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tb->sync();
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tb->test( 0, 16);
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tb->test( 0, 16);
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tb->test( 16, 0);
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tb->test(-16, 0);
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tb->test( 0, 16);
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tb->test( 0,-16);
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for(int k=0; k<1060; k++) {
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tb->random_test();
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}
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}
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delete qstage;
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delete tb;
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printf("SUCCESS!\n");
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printf("SUCCESS!\n");
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exit(0);
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exit(0);
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}
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}
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