| Line 6... |
Line 6... |
//
|
//
|
// Purpose: This is the main module in the General Purpose FPGA FFT
|
// Purpose: This is the main module in the General Purpose FPGA FFT
|
// implementation. As such, all other modules are subordinate
|
// implementation. As such, all other modules are subordinate
|
// to this one. This module accomplish a fixed size Complex FFT on
|
// to this one. This module accomplish a fixed size Complex FFT on
|
// 2048 data points.
|
// 2048 data points.
|
// The FFT is fully pipelined, and accepts as inputs two complex two's
|
// The FFT is fully pipelined, and accepts as inputs one complex two's
|
// complement samples per clock.
|
// complement sample per clock.
|
//
|
//
|
// Parameters:
|
// Parameters:
|
// i_clk The clock. All operations are synchronous with this clock.
|
// i_clk The clock. All operations are synchronous with this clock.
|
// i_reset Synchronous reset, active high. Setting this line will
|
// i_reset Synchronous reset, active high. Setting this line will
|
// force the reset of all of the internals to this routine.
|
// force the reset of all of the internals to this routine.
|
// Further, following a reset, the o_sync line will go
|
// Further, following a reset, the o_sync line will go
|
// high the same time the first output sample is valid.
|
// high the same time the first output sample is valid.
|
// i_ce A clock enable line. If this line is set, this module
|
// i_ce A clock enable line. If this line is set, this module
|
// will accept two complex values as inputs, and produce
|
// will accept one complex input value, and produce
|
// two (possibly empty) complex values as outputs.
|
// one (possibly empty) complex output value.
|
// i_left The first of two complex input samples. This value is split
|
// i_sample The complex input sample. This value is split
|
// into two two's complement numbers, 15 bits each, with
|
// into two two's complement numbers, 15 bits each, with
|
// the real portion in the high order bits, and the
|
// the real portion in the high order bits, and the
|
// imaginary portion taking the bottom 15 bits.
|
// imaginary portion taking the bottom 15 bits.
|
// i_right This is the same thing as i_left, only this is the second of
|
// o_result The output result, of the same format as i_sample,
|
// two such samples. Hence, i_left would contain input
|
|
// sample zero, i_right would contain sample one. On the
|
|
// next clock i_left would contain input sample two,
|
|
// i_right number three and so forth.
|
|
// o_left The first of two output samples, of the same format as i_left,
|
|
// only having 21 bits for each of the real and imaginary
|
// only having 21 bits for each of the real and imaginary
|
// components, leading to 42 bits total.
|
// components, leading to 42 bits total.
|
// o_right The second of two output samples produced each clock. This has
|
// o_sync A one bit output indicating the first sample of the FFT frame.
|
// the same format as o_left.
|
// It also indicates the first valid sample out of the FFT
|
// o_sync A one bit output indicating the first valid sample produced by
|
// on the first frame.
|
// this FFT following a reset. Ever after, this will
|
|
// indicate the first sample of an FFT frame.
|
|
//
|
//
|
// Arguments: This file was computer generated using the following command
|
// Arguments: This file was computer generated using the following command
|
// line:
|
// line:
|
//
|
//
|
// % ./fftgen -v -d ../rtl -f 2048 -2 -p 0 -n 15 -a ../bench/cpp/fftsize.h
|
// % ./fftgen -v -d ../rtl -f 2048 -1 -k 1 -p 0 -n 15 -a ../bench/cpp/fftsize.h
|
|
//
|
|
// This core will use hardware accelerated multiplies (DSPs)
|
|
// for 0 of the 11 stages
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015-2018, Gisselquist Technology, LLC
|
// Copyright (C) 2015-2018, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This file is part of the general purpose pipelined FFT project.
|
// modify it under the terms of the GNU General Public License as published
|
//
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// The pipelined FFT project is free software (firmware): you can redistribute
|
// your option) any later version.
|
// it and/or modify it under the terms of the GNU Lesser General Public License
|
//
|
// as published by the Free Software Foundation, either version 3 of the
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// License, or (at your option) any later version.
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
//
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// The pipelined FFT project is distributed in the hope that it will be useful,
|
// for more details.
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
//
|
// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
|
// You should have received a copy of the GNU General Public License along
|
// General Public License for more details.
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
//
|
// target there if the PDF file isn't present.) If not, see
|
// You should have received a copy of the GNU Lesser General Public License
|
|
// along with this program. (It's in the $(ROOT)/doc directory. Run make
|
|
// with no target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
|
// <http://www.gnu.org/licenses/> for a copy.
|
//
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: LGPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/lgpl.html
|
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
`default_nettype none
|
`default_nettype none
|
//
|
//
|
//
|
//
|
//
|
//
|
module fftmain(i_clk, i_reset, i_ce,
|
module fftmain(i_clk, i_reset, i_ce,
|
i_left, i_right,
|
i_sample, o_result, o_sync);
|
o_left, o_right, o_sync);
|
// The bit-width of the input, IWIDTH, output, OWIDTH, and the log
|
parameter IWIDTH=15, OWIDTH=21, LGWIDTH=11;
|
// of the FFT size. These are localparams, rather than parameters,
|
|
// because once the core has been generated, they can no longer be
|
|
// changed. (These values can be adjusted by running the core
|
|
// generator again.) The reason is simply that these values have
|
|
// been hardwired into the core at several places.
|
|
localparam IWIDTH=15, OWIDTH=21, LGWIDTH=11;
|
//
|
//
|
input i_clk, i_reset, i_ce;
|
input wire i_clk, i_reset, i_ce;
|
//
|
//
|
input [(2*IWIDTH-1):0] i_left, i_right;
|
input wire [(2*IWIDTH-1):0] i_sample;
|
output reg [(2*OWIDTH-1):0] o_left, o_right;
|
output reg [(2*OWIDTH-1):0] o_result;
|
output reg o_sync;
|
output reg o_sync;
|
|
|
|
|
// Outputs of the FFT, ready for bit reversal.
|
// Outputs of the FFT, ready for bit reversal.
|
wire [(2*OWIDTH-1):0] br_left, br_right;
|
wire [(2*OWIDTH-1):0] br_sample;
|
|
|
|
|
wire w_s2048;
|
wire w_s2048;
|
// verilator lint_off UNUSED
|
wire [31:0] w_d2048;
|
wire w_os2048;
|
fftstage #(IWIDTH,IWIDTH+4,16,10,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_2048.hex")
|
wire [31:0] w_e2048, w_o2048;
|
stage_2048(i_clk, i_reset, i_ce,
|
fftstage #(IWIDTH,IWIDTH+4,16,11,9,0,
|
(!i_reset), i_sample, w_d2048, w_s2048);
|
0, 1, "cmem_e4096.hex")
|
|
stage_e2048(i_clk, i_reset, i_ce,
|
|
(!i_reset), i_left, w_e2048, w_s2048);
|
|
fftstage #(IWIDTH,IWIDTH+4,16,11,9,0,
|
|
0, 1, "cmem_o4096.hex")
|
|
stage_o2048(i_clk, i_reset, i_ce,
|
|
(!i_reset), i_right, w_o2048, w_os2048);
|
|
|
|
|
|
wire w_s1024;
|
wire w_s1024;
|
// verilator lint_off UNUSED
|
wire [33:0] w_d1024;
|
wire w_os1024;
|
fftstage #(16,20,17,9,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_1024.hex")
|
wire [33:0] w_e1024, w_o1024;
|
stage_1024(i_clk, i_reset, i_ce,
|
fftstage #(16,20,17,11,8,0,
|
w_s2048, w_d2048, w_d1024, w_s1024);
|
0, 1, "cmem_e2048.hex")
|
|
stage_e1024(i_clk, i_reset, i_ce,
|
|
w_s2048, w_e2048, w_e1024, w_s1024);
|
|
fftstage #(16,20,17,11,8,0,
|
|
0, 1, "cmem_o2048.hex")
|
|
stage_o1024(i_clk, i_reset, i_ce,
|
|
w_s2048, w_o2048, w_o1024, w_os1024);
|
|
|
|
wire w_s512;
|
wire w_s512;
|
// verilator lint_off UNUSED
|
wire [33:0] w_d512;
|
wire w_os512;
|
fftstage #(17,21,17,8,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_512.hex")
|
wire [33:0] w_e512, w_o512;
|
stage_512(i_clk, i_reset, i_ce,
|
fftstage #(17,21,17,11,7,0,
|
w_s1024, w_d1024, w_d512, w_s512);
|
0, 1, "cmem_e1024.hex")
|
|
stage_e512(i_clk, i_reset, i_ce,
|
|
w_s1024, w_e1024, w_e512, w_s512);
|
|
fftstage #(17,21,17,11,7,0,
|
|
0, 1, "cmem_o1024.hex")
|
|
stage_o512(i_clk, i_reset, i_ce,
|
|
w_s1024, w_o1024, w_o512, w_os512);
|
|
|
|
wire w_s256;
|
wire w_s256;
|
// verilator lint_off UNUSED
|
wire [35:0] w_d256;
|
wire w_os256;
|
fftstage #(17,21,18,7,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_256.hex")
|
wire [35:0] w_e256, w_o256;
|
stage_256(i_clk, i_reset, i_ce,
|
fftstage #(17,21,18,11,6,0,
|
w_s512, w_d512, w_d256, w_s256);
|
0, 1, "cmem_e512.hex")
|
|
stage_e256(i_clk, i_reset, i_ce,
|
|
w_s512, w_e512, w_e256, w_s256);
|
|
fftstage #(17,21,18,11,6,0,
|
|
0, 1, "cmem_o512.hex")
|
|
stage_o256(i_clk, i_reset, i_ce,
|
|
w_s512, w_o512, w_o256, w_os256);
|
|
|
|
wire w_s128;
|
wire w_s128;
|
// verilator lint_off UNUSED
|
wire [35:0] w_d128;
|
wire w_os128;
|
fftstage #(18,22,18,6,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_128.hex")
|
wire [35:0] w_e128, w_o128;
|
stage_128(i_clk, i_reset, i_ce,
|
fftstage #(18,22,18,11,5,0,
|
w_s256, w_d256, w_d128, w_s128);
|
0, 1, "cmem_e256.hex")
|
|
stage_e128(i_clk, i_reset, i_ce,
|
|
w_s256, w_e256, w_e128, w_s128);
|
|
fftstage #(18,22,18,11,5,0,
|
|
0, 1, "cmem_o256.hex")
|
|
stage_o128(i_clk, i_reset, i_ce,
|
|
w_s256, w_o256, w_o128, w_os128);
|
|
|
|
wire w_s64;
|
wire w_s64;
|
// verilator lint_off UNUSED
|
wire [37:0] w_d64;
|
wire w_os64;
|
fftstage #(18,22,19,5,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_64.hex")
|
wire [37:0] w_e64, w_o64;
|
stage_64(i_clk, i_reset, i_ce,
|
fftstage #(18,22,19,11,4,0,
|
w_s128, w_d128, w_d64, w_s64);
|
0, 1, "cmem_e128.hex")
|
|
stage_e64(i_clk, i_reset, i_ce,
|
|
w_s128, w_e128, w_e64, w_s64);
|
|
fftstage #(18,22,19,11,4,0,
|
|
0, 1, "cmem_o128.hex")
|
|
stage_o64(i_clk, i_reset, i_ce,
|
|
w_s128, w_o128, w_o64, w_os64);
|
|
|
|
wire w_s32;
|
wire w_s32;
|
// verilator lint_off UNUSED
|
wire [37:0] w_d32;
|
wire w_os32;
|
fftstage #(19,23,19,4,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_32.hex")
|
wire [37:0] w_e32, w_o32;
|
stage_32(i_clk, i_reset, i_ce,
|
fftstage #(19,23,19,11,3,0,
|
w_s64, w_d64, w_d32, w_s32);
|
0, 1, "cmem_e64.hex")
|
|
stage_e32(i_clk, i_reset, i_ce,
|
|
w_s64, w_e64, w_e32, w_s32);
|
|
fftstage #(19,23,19,11,3,0,
|
|
0, 1, "cmem_o64.hex")
|
|
stage_o32(i_clk, i_reset, i_ce,
|
|
w_s64, w_o64, w_o32, w_os32);
|
|
|
|
wire w_s16;
|
wire w_s16;
|
// verilator lint_off UNUSED
|
wire [39:0] w_d16;
|
wire w_os16;
|
fftstage #(19,23,20,3,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_16.hex")
|
wire [39:0] w_e16, w_o16;
|
stage_16(i_clk, i_reset, i_ce,
|
fftstage #(19,23,20,11,2,0,
|
w_s32, w_d32, w_d16, w_s16);
|
0, 1, "cmem_e32.hex")
|
|
stage_e16(i_clk, i_reset, i_ce,
|
|
w_s32, w_e32, w_e16, w_s16);
|
|
fftstage #(19,23,20,11,2,0,
|
|
0, 1, "cmem_o32.hex")
|
|
stage_o16(i_clk, i_reset, i_ce,
|
|
w_s32, w_o32, w_o16, w_os16);
|
|
|
|
wire w_s8;
|
wire w_s8;
|
// verilator lint_off UNUSED
|
wire [39:0] w_d8;
|
wire w_os8;
|
fftstage #(20,24,20,2,0,
|
// verilator lint_on UNUSED
|
0, 1, "cmem_8.hex")
|
wire [39:0] w_e8, w_o8;
|
stage_8(i_clk, i_reset, i_ce,
|
fftstage #(20,24,20,11,1,0,
|
w_s16, w_d16, w_d8, w_s8);
|
0, 1, "cmem_e16.hex")
|
|
stage_e8(i_clk, i_reset, i_ce,
|
|
w_s16, w_e16, w_e8, w_s8);
|
|
fftstage #(20,24,20,11,1,0,
|
|
0, 1, "cmem_o16.hex")
|
|
stage_o8(i_clk, i_reset, i_ce,
|
|
w_s16, w_o16, w_o8, w_os8);
|
|
|
|
wire w_s4;
|
wire w_s4;
|
// verilator lint_off UNUSED
|
wire [41:0] w_d4;
|
wire w_os4;
|
qtrstage #(20,21,11,0,0) stage_4(i_clk, i_reset, i_ce,
|
// verilator lint_on UNUSED
|
w_s8, w_d8, w_d4, w_s4);
|
wire [41:0] w_e4, w_o4;
|
|
qtrstage #(20,21,11,0,0,0) stage_e4(i_clk, i_reset, i_ce,
|
|
w_s8, w_e8, w_e4, w_s4);
|
|
qtrstage #(20,21,11,1,0,0) stage_o4(i_clk, i_reset, i_ce,
|
|
w_s8, w_o8, w_o4, w_os4);
|
|
wire w_s2;
|
wire w_s2;
|
wire [41:0] w_e2, w_o2;
|
wire [41:0] w_d2;
|
laststage #(21,21,0) stage_2(i_clk, i_reset, i_ce,
|
laststage #(21,21,0) stage_2(i_clk, i_reset, i_ce,
|
w_s4, w_e4, w_o4, w_e2, w_o2, w_s2);
|
w_s4, w_d4, w_d2, w_s2);
|
|
|
|
|
// Prepare for a (potential) bit-reverse stage.
|
// Prepare for a (potential) bit-reverse stage.
|
assign br_left = w_e2;
|
assign br_sample= w_d2;
|
assign br_right = w_o2;
|
|
|
|
wire br_start;
|
wire br_start;
|
reg r_br_started;
|
reg r_br_started;
|
initial r_br_started = 1'b0;
|
initial r_br_started = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 248... |
Line 182... |
r_br_started <= r_br_started || w_s2;
|
r_br_started <= r_br_started || w_s2;
|
assign br_start = r_br_started || w_s2;
|
assign br_start = r_br_started || w_s2;
|
|
|
// Now for the bit-reversal stage.
|
// Now for the bit-reversal stage.
|
wire br_sync;
|
wire br_sync;
|
wire [(2*OWIDTH-1):0] br_o_left, br_o_right;
|
wire [(2*OWIDTH-1):0] br_o_result;
|
bitreverse #(11,21)
|
bitreverse #(11,21)
|
revstage(i_clk, i_reset,
|
revstage(i_clk, i_reset,
|
(i_ce & br_start), br_left, br_right,
|
(i_ce & br_start), br_sample,
|
br_o_left, br_o_right, br_sync);
|
br_o_result, br_sync);
|
|
|
|
|
// Last clock: Register our outputs, we're done.
|
// Last clock: Register our outputs, we're done.
|
initial o_sync = 1'b0;
|
initial o_sync = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 265... |
Line 199... |
else if (i_ce)
|
else if (i_ce)
|
o_sync <= br_sync;
|
o_sync <= br_sync;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_ce)
|
begin
|
o_result <= br_o_result;
|
o_left <= br_o_left;
|
|
o_right <= br_o_right;
|
|
end
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
