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//
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//
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// Project: A General Purpose Pipelined FFT Implementation
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// Project: A General Purpose Pipelined FFT Implementation
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//
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//
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// Purpose: This is part of an FPGA implementation that will process
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// Purpose: This is part of an FPGA implementation that will process
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// the final stage of a decimate-in-frequency FFT, running
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// the final stage of a decimate-in-frequency FFT, running
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// through the data at two samples per clock. If you notice from the
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// through the data at one sample per clock.
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// derivation of an FFT, the only time both even and odd samples are
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//
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// used at the same time is in this stage. Therefore, other than this
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// stage and these twiddles, all of the other stages can run two stages
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// at a time at one sample per clock.
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//
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// Operation:
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// Given a stream of values, operate upon them as though they were
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// value pairs, x[2n] and x[2n+1]. The stream begins when n=0, and ends
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// when n=1. When the first x[0] value enters, the synchronization
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// input, i_sync, must be true as well.
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//
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// For this stream, produce outputs
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// y[2n ] = x[2n] + x[2n+1], and
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// y[2n+1] = x[2n] - x[2n+1]
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//
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// When y[0] is output, a synchronization bit o_sync will be true as
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// well, otherwise it will be zero.
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//
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//
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// In this implementation, the output is valid one clock after the input
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// is valid. The output also accumulates one bit above and beyond the
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// number of bits in the input.
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//
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// i_clk A system clock
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// i_reset A synchronous reset
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// i_ce Circuit enable--nothing happens unless this line is high
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// i_sync A synchronization signal, high once per FFT at the start
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// i_left The first (even) complex sample input. The higher order
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// bits contain the real portion, low order bits the
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// imaginary portion, all in two's complement.
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// i_right The next (odd) complex sample input, same format as
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// i_left.
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// o_left The first (even) complex output.
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// o_right The next (odd) complex output.
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// o_sync Output synchronization signal.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This file is part of the general purpose pipelined FFT project.
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// modify it under the terms of the GNU General Public License as published
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//
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// by the Free Software Foundation, either version 3 of the License, or (at
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// The pipelined FFT project is free software (firmware): you can redistribute
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// your option) any later version.
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// it and/or modify it under the terms of the GNU Lesser General Public License
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//
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// as published by the Free Software Foundation, either version 3 of the
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// License, or (at your option) any later version.
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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//
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// The pipelined FFT project is distributed in the hope that it will be useful,
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// for more details.
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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//
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// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
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// You should have received a copy of the GNU General Public License along
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// General Public License for more details.
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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//
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// target there if the PDF file isn't present.) If not, see
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/lgpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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`default_nettype none
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//
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//
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module laststage(i_clk, i_reset, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);
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module laststage(i_clk, i_reset, i_ce, i_sync, i_val, o_val, o_sync);
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parameter IWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;
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parameter IWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;
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input i_clk, i_reset, i_ce, i_sync;
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input wire i_clk, i_reset, i_ce, i_sync;
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input [(2*IWIDTH-1):0] i_left, i_right;
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input wire [(2*IWIDTH-1):0] i_val;
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output reg [(2*OWIDTH-1):0] o_left, o_right;
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output wire [(2*OWIDTH-1):0] o_val;
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output reg o_sync;
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output reg o_sync;
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wire signed [(IWIDTH-1):0] i_in_0r, i_in_0i, i_in_1r, i_in_1i;
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reg signed [(IWIDTH-1):0] m_r, m_i;
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assign i_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)];
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wire signed [(IWIDTH-1):0] i_r, i_i;
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assign i_in_0i = i_left[(IWIDTH-1):0];
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assign i_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)];
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assign i_in_1i = i_right[(IWIDTH-1):0];
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wire [(OWIDTH-1):0] o_out_0r, o_out_0i,
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o_out_1r, o_out_1i;
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// Handle a potential rounding situation, when IWIDTH>=OWIDTH.
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assign i_r = i_val[(2*IWIDTH-1):(IWIDTH)];
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assign i_i = i_val[(IWIDTH-1):0];
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// Don't forget that we accumulate a bit by adding two values
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// together. Therefore our intermediate value must have one more
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// bit than the two originals.
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reg signed [(IWIDTH):0] rnd_r, rnd_i, sto_r, sto_i;
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reg wait_for_sync, stage;
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reg [1:0] sync_pipe;
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// As with any register connected to the sync pulse, these must
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initial wait_for_sync = 1'b1;
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// have initial values and be reset on the i_reset signal.
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initial stage = 1'b0;
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// Other data values need only restrict their updates to i_ce
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// enabled clocks, but sync's must obey resets and initial
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// conditions as well.
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reg rnd_sync, r_sync;
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initial rnd_sync = 1'b0; // Sync into rounding
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initial r_sync = 1'b0; // Sync coming out
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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begin
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begin
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rnd_sync <= 1'b0;
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wait_for_sync <= 1'b1;
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r_sync <= 1'b0;
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stage <= 1'b0;
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end else if (i_ce)
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end else if ((i_ce)&&((!wait_for_sync)||(i_sync))&&(!stage))
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begin
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begin
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rnd_sync <= i_sync;
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wait_for_sync <= 1'b0;
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r_sync <= rnd_sync;
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//
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end
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stage <= 1'b1;
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//
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end else if (i_ce)
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stage <= 1'b0;
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// As with other variables, these are really only updated when in
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initial sync_pipe = 0;
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// the processing pipeline, after the first i_sync. However, to
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always @(posedge i_clk)
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// eliminate as much unnecessary logic as possible, we toggle
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if (i_reset)
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// these any time the i_ce line is enabled, and don't reset.
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sync_pipe <= 0;
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// them on i_reset.
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else if (i_ce)
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// Don't forget that we accumulate a bit by adding two values
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sync_pipe <= { sync_pipe[0], i_sync };
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// together. Therefore our intermediate value must have one more
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// bit than the two originals.
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initial o_sync = 1'b0;
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reg signed [(IWIDTH):0] rnd_in_0r, rnd_in_0i;
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always @(posedge i_clk)
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reg signed [(IWIDTH):0] rnd_in_1r, rnd_in_1i;
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if (i_reset)
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o_sync <= 1'b0;
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else if (i_ce)
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o_sync <= sync_pipe[1];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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if (!stage)
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begin
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// Clock 1
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m_r <= i_r;
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m_i <= i_i;
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// Clock 3
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rnd_r <= sto_r;
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rnd_i <= sto_i;
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//
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end else begin
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// Clock 2
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rnd_r <= m_r + i_r;
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rnd_i <= m_i + i_i;
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//
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//
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rnd_in_0r <= i_in_0r + i_in_1r;
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sto_r <= m_r - i_r;
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rnd_in_0i <= i_in_0i + i_in_1i;
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sto_i <= m_i - i_i;
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//
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rnd_in_1r <= i_in_0r - i_in_1r;
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rnd_in_1i <= i_in_0i - i_in_1i;
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//
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//
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end
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end
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end
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// Now that we have our results, let's round them and report them
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wire signed [(OWIDTH-1):0] o_r, o_i;
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_0r(i_clk, i_ce,
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_r(i_clk, i_ce, rnd_r, o_r);
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rnd_in_0r, o_out_0r);
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_i(i_clk, i_ce, rnd_i, o_i);
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_0i(i_clk, i_ce,
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assign o_val = { o_r, o_i };
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rnd_in_0i, o_out_0i);
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_1r(i_clk, i_ce,
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`ifdef FORMAL
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rnd_in_1r, o_out_1r);
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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convround #(IWIDTH+1,OWIDTH,SHIFT) do_rnd_1i(i_clk, i_ce,
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`ifdef LASTSTAGE
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rnd_in_1i, o_out_1i);
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always @(posedge i_clk)
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assume((i_ce)||($past(i_ce))||($past(i_ce,2)));
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`endif
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initial assert(IWIDTH+1 == OWIDTH);
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// Prior versions of this routine did not include the extra
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reg signed [IWIDTH-1:0] f_piped_real [0:3];
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// clock and register/flip-flops that this routine requires.
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reg signed [IWIDTH-1:0] f_piped_imag [0:3];
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// These are placed in here to correct a bug in Verilator, that
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// otherwise struggles. (Hopefully this will fix the problem ...)
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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o_left <= { o_out_0r, o_out_0i };
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f_piped_real[0] <= i_val[2*IWIDTH-1:IWIDTH];
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o_right <= { o_out_1r, o_out_1i };
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f_piped_imag[0] <= i_val[ IWIDTH-1:0];
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f_piped_real[1] <= f_piped_real[0];
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f_piped_imag[1] <= f_piped_imag[0];
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f_piped_real[2] <= f_piped_real[1];
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f_piped_imag[2] <= f_piped_imag[1];
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f_piped_real[3] <= f_piped_real[2];
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f_piped_imag[3] <= f_piped_imag[2];
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end
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end
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initial o_sync = 1'b0; // Final sync coming out of module
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wire f_syncd;
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reg f_rsyncd;
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initial f_rsyncd = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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o_sync <= 1'b0;
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f_rsyncd <= 1'b0;
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else if (i_ce)
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else if (!f_rsyncd)
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o_sync <= r_sync;
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f_rsyncd <= o_sync;
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assign f_syncd = (f_rsyncd)||(o_sync);
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reg f_state;
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initial f_state = 0;
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always @(posedge i_clk)
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if (i_reset)
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f_state <= 0;
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else if ((i_ce)&&((!wait_for_sync)||(i_sync)))
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f_state <= f_state + 1;
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always @(*)
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if (f_state != 0)
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assume(!i_sync);
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always @(*)
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assert(stage == f_state[0]);
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always @(posedge i_clk)
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if ((f_state == 1'b1)&&(f_syncd))
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begin
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assert(o_r == f_piped_real[2] + f_piped_real[1]);
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assert(o_i == f_piped_imag[2] + f_piped_imag[1]);
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end
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always @(posedge i_clk)
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if ((f_state == 1'b0)&&(f_syncd))
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begin
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assert(!o_sync);
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assert(o_r == f_piped_real[3] - f_piped_real[2]);
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assert(o_i == f_piped_imag[3] - f_piped_imag[2]);
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end
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always @(*)
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if (wait_for_sync)
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begin
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assert(!f_rsyncd);
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assert(!o_sync);
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assert(f_state == 0);
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end
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`endif // FORMAL
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endmodule
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endmodule
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No newline at end of file
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