| Line 103... |
Line 103... |
"module\tqtrstage(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n"
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"module\tqtrstage(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync);\n"
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"\tparameter IWIDTH=16, OWIDTH=IWIDTH+1;\n"
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"\tparameter IWIDTH=16, OWIDTH=IWIDTH+1;\n"
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"\t// Parameters specific to the core that should be changed when this\n"
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"\t// Parameters specific to the core that should be changed when this\n"
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"\t// core is built ... Note that the minimum LGSPAN is 2. Smaller \n"
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"\t// core is built ... Note that the minimum LGSPAN is 2. Smaller \n"
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"\t// spans must use the fftdoubles stage.\n"
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"\t// spans must use the fftdoubles stage.\n"
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"\tparameter\tLGWIDTH=8, ODD=0, INVERSE=0,SHIFT=0,ROUND=0;\n"
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"\tparameter\tLGWIDTH=8, ODD=0, INVERSE=0,SHIFT=0,ROUND=1;\n"
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"\tinput\t i_clk, i_rst, i_ce, i_sync;\n"
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"\tinput\t i_clk, i_rst, i_ce, i_sync;\n"
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"\tinput\t [(2*IWIDTH-1):0] i_data;\n"
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"\tinput\t [(2*IWIDTH-1):0] i_data;\n"
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"\toutput\treg [(2*OWIDTH-1):0] o_data;\n"
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"\toutput\treg [(2*OWIDTH-1):0] o_data;\n"
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"\toutput\treg o_sync;\n"
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"\toutput\treg o_sync;\n"
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"\t\n");
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"\t\n");
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| Line 260... |
Line 260... |
"//\n", prjname, creator);
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"//\n", prjname, creator);
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|
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fprintf(fp, "%s", cpyleft);
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fprintf(fp, "%s", cpyleft);
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fprintf(fp,
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fprintf(fp,
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"module\tdblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"
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"module\tdblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"
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"\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n"
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"\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n" // ROUND=1
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"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
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"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
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"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
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"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
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"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
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"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
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"\toutput\treg\t\t\to_sync;\n"
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"\toutput\treg\t\t\to_sync;\n"
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"\n"
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"\n"
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| Line 274... |
Line 274... |
"\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
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"\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
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"\tassign\ti_in_1i = i_right[(IWIDTH-1):0]; \n"
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"\tassign\ti_in_1i = i_right[(IWIDTH-1):0]; \n"
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"\twire\t[(OWIDTH-1):0]\t\to_out_0r, o_out_0i,\n"
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"\twire\t[(OWIDTH-1):0]\t\to_out_0r, o_out_0i,\n"
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"\t\t\t\t\to_out_1r, o_out_1i;\n"
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"\t\t\t\t\to_out_1r, o_out_1i;\n"
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"\n"
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"\n"
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"\n"
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// "\t// Handle a potential rounding situation, when IWIDTH=OWIDTH.\n"
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//"\n"
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// "\twire\tsigned\t[(IWIDTH-1):0]\trnd;\n"
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//"\n"
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// "\tgenerate\n"
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// "\tif ((ROUND==1)&&(IWIDTH==OWIDTH))\n"
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// "\t\tassign rnd = { {(IWIDTH-1){1'b0}}, 1'b1 };\n"
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// "\telse\n"
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// "\t\tassign rnd = { {(IWIDTH){1'b0}} };\n"
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// "\tendgenerate\n"
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"\n"
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"\t// Don't forget that we accumulate a bit by adding two values\n"
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"\t// Don't forget that we accumulate a bit by adding two values\n"
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"\t// together. Therefore our intermediate value must have one more\n"
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"\t// together. Therefore our intermediate value must have one more\n"
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"\t// bit than the two originals.\n"
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"\t// bit than the two originals.\n"
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"\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
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"\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
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"\n"
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"\n"
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| Line 288... |
Line 300... |
"\t\t\twait_for_sync <= 1'b1;\n"
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"\t\t\twait_for_sync <= 1'b1;\n"
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"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
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"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
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"\t\tbegin\n"
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"\t\tbegin\n"
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"\t\t\twait_for_sync <= 1'b0;\n"
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"\t\t\twait_for_sync <= 1'b0;\n"
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\tout_0r <= i_in_0r + i_in_1r;\n"
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"\t\t\tout_0r <= i_in_0r + i_in_1r;\n" // + rnd
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"\t\t\tout_0i <= i_in_0i + i_in_1i;\n"
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"\t\t\tout_0i <= i_in_0i + i_in_1i;\n" // + rnd
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\tout_1r <= i_in_0r - i_in_1r;\n"
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"\t\t\tout_1r <= i_in_0r - i_in_1r;\n" // + rnd
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"\t\t\tout_1i <= i_in_0i - i_in_1i;\n"
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"\t\t\tout_1i <= i_in_0i - i_in_1i;\n" // + rnd
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\to_sync <= i_sync;\n"
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"\t\t\to_sync <= i_sync;\n"
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"\t\tend\n"
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"\t\tend\n"
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"\n"
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"\n"
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"\t// Now, if the master control program doesn't want to keep all of\n"
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"\t// Now, if the master control program doesn't want to keep all of\n"
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| Line 632... |
Line 644... |
"\t\to_left, o_right, o_aux);\n"
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"\t\to_left, o_right, o_aux);\n"
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"\t// Public changeable parameters ...\n"
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"\t// Public changeable parameters ...\n"
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"\tparameter IWIDTH=%d,CWIDTH=IWIDTH+%d,OWIDTH=IWIDTH+1;\n"
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"\tparameter IWIDTH=%d,CWIDTH=IWIDTH+%d,OWIDTH=IWIDTH+1;\n"
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"\t// Parameters specific to the core that should not be changed.\n"
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"\t// Parameters specific to the core that should not be changed.\n"
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"\tparameter MPYDELAY=%d'd%d, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
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"\tparameter MPYDELAY=%d'd%d, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
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"\t\t\tSHIFT=0, ROUND=0;\n"
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"\t\t\tSHIFT=0, ROUND=1;\n"
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"\t// The LGDELAY should be the base two log of the MPYDELAY. If\n"
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"\t// The LGDELAY should be the base two log of the MPYDELAY. If\n"
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"\t// this value is fractional, then round up to the nearest\n"
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"\t// this value is fractional, then round up to the nearest\n"
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"\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
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"\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
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"\tparameter\tLGDELAY=%d;\n"
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"\tparameter\tLGDELAY=%d;\n"
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"\tinput\t\ti_clk, i_rst, i_ce;\n"
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"\tinput\t\ti_clk, i_rst, i_ce;\n"
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| Line 798... |
Line 810... |
"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] b_left_r, b_left_i,\n"
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"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] b_left_r, b_left_i,\n"
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"\t\t\t\t\t\tb_right_r, b_right_i;\n"
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"\t\t\t\t\t\tb_right_r, b_right_i;\n"
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"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
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"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
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"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] rnd;\n"
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"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] rnd;\n"
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"\tgenerate\n"
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"\tgenerate\n"
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"\tif ((~ROUND)||(CWIDTH+IWIDTH-OWIDTH-SHIFT<1))\n"
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"\tif ((ROUND==0)||(CWIDTH+IWIDTH-OWIDTH-SHIFT<1))\n"
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"\t\tassign rnd = ({(CWIDTH+IWIDTH+3){1'b0}});\n"
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"\t\tassign rnd = ({(CWIDTH+IWIDTH+3){1'b0}});\n"
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"\telse\n"
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"\telse\n"
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"\t\tassign rnd = ({ {(OWIDTH+3+SHIFT){1'b0}},1'b1,\n"
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"\t\tassign rnd = ({ {(OWIDTH+4+SHIFT){1'b0}},1'b1,\n"
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"\t\t\t\t{(CWIDTH+IWIDTH-OWIDTH-SHIFT-1){1'b0}} });\n"
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"\t\t\t\t{((IWIDTH+CWIDTH+3)-(OWIDTH+SHIFT+5)){1'b0}} });\n"
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"\tendgenerate\n"
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"\tendgenerate\n"
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"\n");
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"\n");
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fprintf(fp,
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fprintf(fp,
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"\talways @(posedge i_clk)\n"
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"\talways @(posedge i_clk)\n"
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"\t\tif (i_ce)\n"
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"\t\tif (i_ce)\n"
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