| Line 181... |
Line 181... |
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tomem <= ob_b;\n"
|
"\t\t\t\tomem <= ob_b;\n"
|
"\t\t\t\to_data <= ob_a;\n"
|
"\t\t\t\to_data <= ob_a;\n"
|
"\t\t\tend else\n"
|
"\t\t\tend else\n"
|
"\t\t\t\to_data <= omem;\n"
|
"\t\t\t\to_data <= omem;\n"
|
"\t\t\to_sync <= &(~iaddr[(LGWIDTH-1):3]) && (iaddr[2:0] == 3'b100);\n"
|
"\t\t\t// Don\'t forget in the sync check that we are running\n"
|
|
"\t\t\t// at two clocks per sample. Thus we need to\n"
|
|
"\t\t\t// produce a sync every 2^(LGWIDTH-1) clocks.\n"
|
|
"\t\t\to_sync <= &(~iaddr[(LGWIDTH-2):3]) && (iaddr[2:0] == 3'b100);\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"endmodule\n");
|
"endmodule\n");
|
}
|
}
|
|
|
void build_dblstage(const char *fname) {
|
void build_dblstage(const char *fname) {
|
| Line 215... |
Line 218... |
"// In this implementation, the output is valid one clock after\n"
|
"// In this implementation, the output is valid one clock after\n"
|
"// the input is valid. The output also accumulates one bit\n"
|
"// the input is valid. The output also accumulates one bit\n"
|
"// above and beyond the number of bits in the input.\n"
|
"// above and beyond the number of bits in the input.\n"
|
"// \n"
|
"// \n"
|
"// i_clk A system clock\n"
|
"// i_clk A system clock\n"
|
|
"// i_rst A synchronous reset\n"
|
"// i_ce Circuit enable--nothing happens unless this line is high\n"
|
"// i_ce Circuit enable--nothing happens unless this line is high\n"
|
|
"// i_sync A synchronization signal, high once per FFT at the start\n"
|
"// i_left The first (even) complex sample input. The higher order\n"
|
"// i_left The first (even) complex sample input. The higher order\n"
|
"// bits contain the real portion, low order bits the\n"
|
"// bits contain the real portion, low order bits the\n"
|
"// imaginary portion, all in two\'s complement.\n"
|
"// imaginary portion, all in two\'s complement.\n"
|
"// i_right The next (odd) complex sample input, same format as\n"
|
"// i_right The next (odd) complex sample input, same format as\n"
|
"// i_left.\n"
|
"// i_left.\n"
|
"// o_left The first (even) complex output.\n"
|
"// o_left The first (even) complex output.\n"
|
"// o_right The next (odd) complex output.\n"
|
"// o_right The next (odd) complex output.\n"
|
|
"// o_sync Output synchronization signal.\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp,
|
fprintf(fp,
|
"module dblstage(i_clk, i_ce, i_left, i_right, o_left, o_right);\n"
|
"module dblstage(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync);\n"
|
"\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n"
|
"\tparameter\tIWIDTH=16,OWIDTH=IWIDTH+1, SHIFT=0;\n"
|
"\tinput\t\ti_clk, i_ce;\n"
|
"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
|
"\toutput\twire [(2*OWIDTH-1):0]\to_left, o_right;\n"
|
"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
|
|
"\toutput\treg\t\t\to_sync;\n"
|
"\n"
|
"\n"
|
"\twire\tsigned\t[(IWIDTH-1):0]\ti_in_0r, i_in_0i, i_in_1r, i_in_1i;\n"
|
"\twire\tsigned\t[(IWIDTH-1):0]\ti_in_0r, i_in_0i, i_in_1r, i_in_1i;\n"
|
"\tassign\ti_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)]; \n"
|
"\tassign\ti_in_0r = i_left[(2*IWIDTH-1):(IWIDTH)]; \n"
|
"\tassign\ti_in_0i = i_left[(IWIDTH-1):0]; \n"
|
"\tassign\ti_in_0i = i_left[(IWIDTH-1):0]; \n"
|
"\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
|
"\tassign\ti_in_1r = i_right[(2*IWIDTH-1):(IWIDTH)]; \n"
|
| Line 247... |
Line 254... |
"\t// Don't forget that we accumulate a bit by adding two values\n"
|
"\t// Don't forget that we accumulate a bit by adding two values\n"
|
"\t// together. Therefore our intermediate value must have one more\n"
|
"\t// together. Therefore our intermediate value must have one more\n"
|
"\t// bit than the two originals.\n"
|
"\t// bit than the two originals.\n"
|
"\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
|
"\treg\t[IWIDTH:0]\tout_0r, out_0i, out_1r, out_1i;\n"
|
"\n"
|
"\n"
|
|
"\treg\twait_for_sync;\n"
|
|
"\n"
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_ce)\n"
|
"\t\tif (i_rst)\n"
|
|
"\t\t\twait_for_sync <= 1'b1;\n"
|
|
"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
|
"\t\t\twait_for_sync <= 1'b0;\n"
|
|
"\t\t\t//\n"
|
"\t\t\tout_0r <= i_in_0r + i_in_1r;\n"
|
"\t\t\tout_0r <= i_in_0r + i_in_1r;\n"
|
"\t\t\tout_0i <= i_in_0i + i_in_1i;\n"
|
"\t\t\tout_0i <= i_in_0i + i_in_1i;\n"
|
"\t\t\t//\n"
|
"\t\t\t//\n"
|
"\t\t\tout_1r <= i_in_0r - i_in_1r;\n"
|
"\t\t\tout_1r <= i_in_0r - i_in_1r;\n"
|
"\t\t\tout_1i <= i_in_0i - i_in_1i;\n"
|
"\t\t\tout_1i <= i_in_0i - i_in_1i;\n"
|
|
"\t\t\t//\n"
|
|
"\t\t\to_sync <= i_sync;\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\n"
|
"\n"
|
"\t// Now, if the master control program doesn't want to keep all of\n"
|
"\t// Now, if the master control program doesn't want to keep all of\n"
|
"\t// our bits, we can shift down to OWIDTH bits here.\n"
|
"\t// our bits, we can shift down to OWIDTH bits here.\n"
|
"\tassign\to_out_0r = out_0r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
|
"\tassign\to_out_0r = out_0r[(IWIDTH-SHIFT):(IWIDTH+1-OWIDTH-SHIFT)];\n"
|
| Line 586... |
Line 601... |
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
|
fprintf(fp,
|
fprintf(fp,
|
"module\tbutterfly(i_clk, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t// Public changeable parameters ...\n"
|
"\t// Public changeable parameters ...\n"
|
"\tparameter IWIDTH=16,CWIDTH=IWIDTH+4,OWIDTH=IWIDTH+1;\n"
|
"\tparameter IWIDTH=16,CWIDTH=IWIDTH+4,OWIDTH=IWIDTH+1;\n"
|
"\t// Parameters specific to the core that should not be changed.\n"
|
"\t// Parameters specific to the core that should not be changed.\n"
|
"\tparameter MPYDELAY=5'd20, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
|
"\tparameter MPYDELAY=5'd20, // (IWIDTH+1 < CWIDTH)?(IWIDTH+4):(CWIDTH+3),\n"
|
"\t\t\tSHIFT=0, ROUND=0;\n"
|
"\t\t\tSHIFT=0, ROUND=0;\n"
|
"\t// The LGDELAY should be the base two log of the MPYDELAY. If\n"
|
"\t// The LGDELAY should be the base two log of the MPYDELAY. If\n"
|
"\t// this value is fractional, then round up to the nearest\n"
|
"\t// this value is fractional, then round up to the nearest\n"
|
"\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
|
"\t// integer: LGDELAY=ceil(log(MPYDELAY)/log(2));\n"
|
"\tparameter\tLGDELAY=5;\n"
|
"\tparameter\tLGDELAY=5;\n"
|
"\tinput\t\ti_clk, i_ce;\n"
|
"\tinput\t\ti_clk, i_rst, i_ce;\n"
|
"\tinput\t\t[(2*CWIDTH-1):0] i_coef;\n"
|
"\tinput\t\t[(2*CWIDTH-1):0] i_coef;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0] i_left, i_right;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0] i_left, i_right;\n"
|
"\tinput\t\ti_aux;\n"
|
"\tinput\t\ti_aux;\n"
|
"\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
|
"\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
|
"\toutput\twire o_aux;\n"
|
"\toutput\twire o_aux;\n"
|
| Line 622... |
Line 637... |
"\n"
|
"\n"
|
"\treg\tsigned\t[(IWIDTH):0]\tr_sum_r, r_sum_i, r_dif_r, r_dif_i;\n"
|
"\treg\tsigned\t[(IWIDTH):0]\tr_sum_r, r_sum_i, r_dif_r, r_dif_i;\n"
|
"\n"
|
"\n"
|
"\treg [(LGDELAY-1):0] fifo_addr;\n"
|
"\treg [(LGDELAY-1):0] fifo_addr;\n"
|
"\twire [(LGDELAY-1):0] fifo_read_addr;\n"
|
"\twire [(LGDELAY-1):0] fifo_read_addr;\n"
|
"\tassign fifo_read_addr = fifo_addr - MPYDELAY;\n"
|
"\tassign\tfifo_read_addr = fifo_addr - MPYDELAY;\n"
|
"\treg [(2*IWIDTH+2):0] fifo_left [ 0:((1<<LGDELAY)-1)];\n"
|
"\treg [(2*IWIDTH+2):0] fifo_left [ 0:((1<<LGDELAY)-1)];\n"
|
|
"\treg\t\t\t\tovalid;\n"
|
"\n");
|
"\n");
|
fprintf(fp,
|
fprintf(fp,
|
"\t// Set up the input to the multiply\n"
|
"\t// Set up the input to the multiply\n"
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_ce)\n"
|
"\t\tif (i_ce)\n"
|
| Line 650... |
Line 666... |
fprintf(fp,
|
fprintf(fp,
|
"\t// Don\'t forget to record the even side, since it doesn\'t need\n"
|
"\t// Don\'t forget to record the even side, since it doesn\'t need\n"
|
"\t// to be multiplied, but yet we still need the results in sync\n"
|
"\t// to be multiplied, but yet we still need the results in sync\n"
|
"\t// with the answer when it is ready.\n"
|
"\t// with the answer when it is ready.\n"
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_ce)\n"
|
"\t\tif (i_rst)\n"
|
|
"\t\tbegin\n"
|
|
"\t\t\tfifo_addr <= 0;\n"
|
|
"\t\t\tovalid <= 1'b0;\n"
|
|
"\t\tend else if (i_ce)\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\t// Need to delay the sum side--nothing else happens\n"
|
"\t\t\t// Need to delay the sum side--nothing else happens\n"
|
"\t\t\t// to it, but it needs to stay synchronized with the\n"
|
"\t\t\t// to it, but it needs to stay synchronized with the\n"
|
"\t\t\t// right side.\n"
|
"\t\t\t// right side.\n"
|
"\t\t\tfifo_left[fifo_addr] <= { r_aux_2, r_sum_r, r_sum_i };\n"
|
"\t\t\tfifo_left[fifo_addr] <= { r_aux_2, r_sum_r, r_sum_i };\n"
|
"\t\t\tfifo_addr <= fifo_addr + 1;\n"
|
"\t\t\tfifo_addr <= fifo_addr + 1;\n"
|
|
"\t\t\tovalid <= (ovalid) || (fifo_addr > MPYDELAY+1);\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\n"
|
"\n"
|
"\twire\tsigned\t[(CWIDTH-1):0] ir_coef_r, ir_coef_i;\n"
|
"\twire\tsigned\t[(CWIDTH-1):0] ir_coef_r, ir_coef_i;\n"
|
"\tassign\tir_coef_r = r_coef_2[(2*CWIDTH-1):CWIDTH];\n"
|
"\tassign\tir_coef_r = r_coef_2[(2*CWIDTH-1):CWIDTH];\n"
|
"\tassign\tir_coef_i = r_coef_2[(CWIDTH-1):0];\n"
|
"\tassign\tir_coef_i = r_coef_2[(CWIDTH-1):0];\n"
|
| Line 774... |
Line 795... |
"\t\t\t// Second clock, round and latch for final clock\n"
|
"\t\t\t// Second clock, round and latch for final clock\n"
|
"\t\t\tb_right_r <= mpy_r + rnd;\n"
|
"\t\t\tb_right_r <= mpy_r + rnd;\n"
|
"\t\t\tb_right_i <= mpy_i + rnd;\n"
|
"\t\t\tb_right_i <= mpy_i + rnd;\n"
|
"\t\t\tb_left_r <= { {2{fifo_r[(IWIDTH+CWIDTH)]}},fifo_r } + rnd;\n"
|
"\t\t\tb_left_r <= { {2{fifo_r[(IWIDTH+CWIDTH)]}},fifo_r } + rnd;\n"
|
"\t\t\tb_left_i <= { {2{fifo_i[(IWIDTH+CWIDTH)]}},fifo_i } + rnd;\n"
|
"\t\t\tb_left_i <= { {2{fifo_i[(IWIDTH+CWIDTH)]}},fifo_i } + rnd;\n"
|
"\t\t\to_aux <= aux;\n"
|
"\t\t\to_aux <= aux & ovalid;\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\n");
|
"\n");
|
fprintf(fp,
|
fprintf(fp,
|
"\t// Final clock--clock and remove unnecessary bits.\n"
|
"\t// Final clock--clock and remove unnecessary bits.\n"
|
"\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
|
"\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
|
| Line 862... |
Line 883... |
fprintf(fstage,
|
fprintf(fstage,
|
"\t// Parameters specific to the core that should be changed when this\n"
|
"\t// Parameters specific to the core that should be changed when this\n"
|
"\t// core is built ... Note that the minimum LGSPAN (the base two log\n"
|
"\t// core is built ... Note that the minimum LGSPAN (the base two log\n"
|
"\t// of the span, or the base two log of the current FFT size) is 3.\n"
|
"\t// of the span, or the base two log of the current FFT size) is 3.\n"
|
"\t// Smaller spans (i.e. the span of 2) must use the dblstage module.\n"
|
"\t// Smaller spans (i.e. the span of 2) must use the dblstage module.\n"
|
"\tparameter\tLGWIDTH=8, LGSPAN=2, LGBDLY=5, BFLYSHIFT=0;\n");
|
"\tparameter\tLGWIDTH=11, LGSPAN=9, LGBDLY=5, BFLYSHIFT=0;\n");
|
fprintf(fstage,
|
fprintf(fstage,
|
"\tinput i_clk, i_rst, i_ce, i_sync;\n"
|
"\tinput i_clk, i_rst, i_ce, i_sync;\n"
|
"\tinput [(2*IWIDTH-1):0] i_data;\n"
|
"\tinput [(2*IWIDTH-1):0] i_data;\n"
|
"\toutput reg [(2*OWIDTH-1):0] o_data;\n"
|
"\toutput reg [(2*OWIDTH-1):0] o_data;\n"
|
"\toutput reg o_sync;\n"
|
"\toutput reg o_sync;\n"
|
| Line 930... |
Line 951... |
*/
|
*/
|
} fclose(cmem);
|
} fclose(cmem);
|
}
|
}
|
|
|
fprintf(fstage,
|
fprintf(fstage,
|
"\treg [(LGWIDTH-1):0] iaddr;\n"
|
"\treg [(LGWIDTH-2):0] iaddr;\n"
|
"\treg [(2*IWIDTH-1):0] imem [0:((1<<LGSPAN)-1)];\n"
|
"\treg [(2*IWIDTH-1):0] imem [0:((1<<LGSPAN)-1)];\n"
|
"\n"
|
"\n"
|
"\treg [(LGSPAN-1):0] oB;\n"
|
"\treg [(LGSPAN-1):0] oB;\n"
|
"\treg [(2*OWIDTH-1):0] omem [0:((1<<LGSPAN)-1)];\n"
|
"\treg [(2*OWIDTH-1):0] omem [0:((1<<LGSPAN)-1)];\n"
|
"\n"
|
"\n"
|
| Line 957... |
Line 978... |
"\n"
|
"\n"
|
"\t\t\t//\n"
|
"\t\t\t//\n"
|
"\t\t\t// Now, we have all the inputs, so let\'s feed the\n"
|
"\t\t\t// Now, we have all the inputs, so let\'s feed the\n"
|
"\t\t\t// butterfly\n"
|
"\t\t\t// butterfly\n"
|
"\t\t\t//\n"
|
"\t\t\t//\n"
|
"\t\t\tif (iaddr[LGSPAN-1])\n"
|
"\t\t\tif (iaddr[LGSPAN])\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\t// One input from memory, ...\n"
|
"\t\t\t\t// One input from memory, ...\n"
|
"\t\t\t\tib_a <= imem[iaddr[(LGSPAN-1):0]];\n"
|
"\t\t\t\tib_a <= imem[iaddr[(LGSPAN-1):0]];\n"
|
"\t\t\t\t// One input clocked in from the top\n"
|
"\t\t\t\t// One input clocked in from the top\n"
|
"\t\t\t\tib_b <= i_data;\n"
|
"\t\t\t\tib_b <= i_data;\n"
|
"\t\t\t\t// Set the sync to true on the very first\n"
|
"\t\t\t\t// Set the sync to true on the very first\n"
|
"\t\t\t\t// valid input in, and hence on the very\n"
|
"\t\t\t\t// valid input in, and hence on the very\n"
|
"\t\t\t\t// first valid data out per FFT.\n"
|
"\t\t\t\t// first valid data out per FFT.\n"
|
"\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN-1)));\n"
|
"\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN)));\n"
|
"\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
|
"\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
|
"\t\t\t\tb_ce <= 1'b1;\n"
|
"\t\t\t\tb_ce <= 1'b1;\n"
|
"\t\t\tend else\n"
|
"\t\t\tend else\n"
|
"\t\t\t\tb_ce <= 1'b0;\n"
|
"\t\t\t\tb_ce <= 1'b0;\n"
|
"\n"
|
"\n"
|
| Line 981... |
Line 1002... |
"\t\t\tbegin // A butterfly output is available\n"
|
"\t\t\tbegin // A butterfly output is available\n"
|
"\t\t\t\tb_started <= 1'b1;\n"
|
"\t\t\t\tb_started <= 1'b1;\n"
|
"\t\t\t\tomem[oB] <= ob_b;\n"
|
"\t\t\t\tomem[oB] <= ob_b;\n"
|
"\t\t\t\toB <= oB+1;\n"
|
"\t\t\t\toB <= oB+1;\n"
|
"\n"
|
"\n"
|
"\t\t\t\tif (ob_sync)\n"
|
"\t\t\t\to_sync <= (ob_sync);\n"
|
"\t\t\t\t\to_sync <= 1'b1;\n"
|
|
"\t\t\t\to_data <= ob_a;\n"
|
"\t\t\t\to_data <= ob_a;\n"
|
"\t\t\tend else if (b_started)\n"
|
"\t\t\tend else if (b_started)\n"
|
"\t\t\tbegin // and keep outputting once you start--at a rate\n"
|
"\t\t\tbegin // and keep outputting once you start--at a rate\n"
|
"\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
|
"\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
|
"\t\t\t\to_data <= omem[oB];\n"
|
"\t\t\t\to_data <= omem[oB];\n"
|
| Line 997... |
Line 1017... |
"\t\tend\n"
|
"\t\tend\n"
|
"\n", (inv)?"i":"");
|
"\n", (inv)?"i":"");
|
fprintf(fstage,
|
fprintf(fstage,
|
"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
|
"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
|
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
|
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
|
"\t\tbfly(i_clk, (b_ce&i_ce), ib_c,\n"
|
"\t\tbfly(i_clk, i_rst, (b_ce&i_ce), ib_c,\n"
|
"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
|
"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
|
"endmodule;\n",
|
"endmodule;\n",
|
lgdelay(nbits, xtra), (1<xtra)?(nbits+4):(nbits+xtra+3));
|
lgdelay(nbits, xtra), (1<xtra)?(nbits+4):(nbits+xtra+3));
|
}
|
}
|
|
|
| Line 1299... |
Line 1319... |
fprintf(vmain, "\t\t\tbr_start <= 1'b0;\n");
|
fprintf(vmain, "\t\t\tbr_start <= 1'b0;\n");
|
fprintf(vmain, "\t\telse if (i_ce)\n");
|
fprintf(vmain, "\t\telse if (i_ce)\n");
|
fprintf(vmain, "\t\t\tbr_start <= 1'b1;\n");
|
fprintf(vmain, "\t\t\tbr_start <= 1'b1;\n");
|
}
|
}
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_ce,\n");
|
fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
|
fprintf(vmain, "\t\t\ti_left, i_right, br_left, br_right);\n");
|
fprintf(vmain, "\t\t\t(~i_rst), i_left, i_right, br_left, br_right);\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
} else {
|
} else {
|
int nbits = nbitsin, dropbit=0;
|
int nbits = nbitsin, dropbit=0;
|
// Always do a first stage
|
// Always do a first stage
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
| Line 1374... |
Line 1394... |
|
|
fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
|
fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
|
fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*obits-1);
|
fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*obits-1);
|
fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
|
fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
|
nbits, obits, lgsize, (inverse)?1:0, dropbit);
|
nbits, obits, lgsize, (inverse)?1:0, dropbit);
|
fprintf(vmain, "\t\t\t\t\t\tw_s4, w_e8, w_e4, w_s4);\n");
|
fprintf(vmain, "\t\t\t\t\t\tw_s8, w_e8, w_e4, w_s4);\n");
|
fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,1,%d,%d)\tstage_o4(i_clk, i_rst, i_ce,\n",
|
fprintf(vmain, "\tqtrstage\t#(%d,%d,%d,1,%d,%d)\tstage_o4(i_clk, i_rst, i_ce,\n",
|
nbits, obits, lgsize, (inverse)?1:0, dropbit);
|
nbits, obits, lgsize, (inverse)?1:0, dropbit);
|
fprintf(vmain, "\t\t\t\t\t\tw_s4, w_o8, w_o4, w_os4);\n");
|
fprintf(vmain, "\t\t\t\t\t\tw_s8, w_o8, w_o4, w_os4);\n");
|
dropbit ^= 1;
|
dropbit ^= 1;
|
nbits = obits;
|
nbits = obits;
|
tmp_size >>= 1; lgtmp--;
|
tmp_size >>= 1; lgtmp--;
|
}
|
}
|
|
|
| Line 1391... |
Line 1411... |
obits = nbitsout;
|
obits = nbitsout;
|
if ((maxbitsout>0)&&(obits > maxbitsout))
|
if ((maxbitsout>0)&&(obits > maxbitsout))
|
obits = maxbitsout;
|
obits = maxbitsout;
|
fprintf(vmain, "\twire\t\tw_s2;\n");
|
fprintf(vmain, "\twire\t\tw_s2;\n");
|
fprintf(vmain, "\twire\t[%d:0]\tw_e2, w_o2;\n", 2*obits-1);
|
fprintf(vmain, "\twire\t[%d:0]\tw_e2, w_o2;\n", 2*obits-1);
|
fprintf(vmain, "\tdblstage\t#(%d,%d,%d)\tstage_2(i_clk, i_ce,\n", nbits, obits,dropbit);
|
fprintf(vmain, "\tdblstage\t#(%d,%d,%d)\tstage_2(i_clk, i_rst, i_ce,\n", nbits, obits,dropbit);
|
fprintf(vmain, "\t\t\t\t\tw_e4, w_o4, w_e2, w_o2);\n");
|
fprintf(vmain, "\t\t\t\t\tw_s4, w_e4, w_o4, w_e2, w_o2, w_s2);\n");
|
|
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
nbits = obits;
|
nbits = obits;
|
}
|
}
|
|
|
