| Line 893... |
Line 893... |
"\toutput reg o_sync;\n"
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"\toutput reg o_sync;\n"
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"\n"
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"\n"
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"\treg wait_for_sync;\n"
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"\treg wait_for_sync;\n"
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"\treg [(2*IWIDTH-1):0] ib_a, ib_b;\n"
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"\treg [(2*IWIDTH-1):0] ib_a, ib_b;\n"
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"\treg [(2*CWIDTH-1):0] ib_c;\n"
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"\treg [(2*CWIDTH-1):0] ib_c;\n"
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"\treg ib_sync, b_ce;\n"
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"\treg ib_sync;\n"
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"\n"
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"\n"
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"\treg b_started;\n"
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"\treg b_started;\n"
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"\twire ob_sync;\n"
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"\twire ob_sync;\n"
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"\twire [(2*OWIDTH-1):0] ob_a, ob_b;\n");
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"\twire [(2*OWIDTH-1):0] ob_a, ob_b;\n");
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fprintf(fstage,
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fprintf(fstage,
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| Line 954... |
Line 954... |
|
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fprintf(fstage,
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fprintf(fstage,
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"\treg [(LGWIDTH-2):0] iaddr;\n"
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"\treg [(LGWIDTH-2):0] iaddr;\n"
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"\treg [(2*IWIDTH-1):0] imem [0:((1<<LGSPAN)-1)];\n"
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"\treg [(2*IWIDTH-1):0] imem [0:((1<<LGSPAN)-1)];\n"
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"\n"
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"\n"
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"\treg [(LGSPAN-1):0] oB;\n"
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"\treg [LGSPAN:0] oB;\n"
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"\treg [(2*OWIDTH-1):0] omem [0:((1<<LGSPAN)-1)];\n"
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"\treg [(2*OWIDTH-1):0] omem [0:((1<<LGSPAN)-1)];\n"
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"\n"
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"\n"
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"\talways @(posedge i_clk)\n"
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"\talways @(posedge i_clk)\n"
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"\t\tif (i_rst)\n"
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"\t\tif (i_rst)\n"
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"\t\tbegin\n"
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"\t\tbegin\n"
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"\t\t\twait_for_sync <= 1'b1;\n"
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"\t\t\twait_for_sync <= 1'b1;\n"
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"\t\t\tiaddr <= 0;\n"
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"\t\t\tiaddr <= 0;\n"
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"\t\t\toB <= 0;\n"
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"\t\t\toB <= 0;\n"
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"\t\t\tb_ce <= 1'b0;\n"
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"\t\t\tib_sync <= 1'b0;\n"
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"\t\t\to_sync <= 1'b0;\n"
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"\t\t\tb_started <= 1'b0;\n"
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"\t\tend\n"
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"\t\tend\n"
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"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
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"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
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"\t\tbegin\n"
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"\t\tbegin\n"
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\t// First step: Record what we\'re not ready to use yet\n"
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"\t\t\t// First step: Record what we\'re not ready to use yet\n"
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| Line 989... |
Line 991... |
"\t\t\t\t// Set the sync to true on the very first\n"
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"\t\t\t\t// Set the sync to true on the very first\n"
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"\t\t\t\t// valid input in, and hence on the very\n"
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"\t\t\t\t// valid input in, and hence on the very\n"
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"\t\t\t\t// first valid data out per FFT.\n"
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"\t\t\t\t// first valid data out per FFT.\n"
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"\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN)));\n"
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"\t\t\t\tib_sync <= (iaddr==(1<<(LGSPAN)));\n"
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"\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
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"\t\t\t\tib_c <= %scmem[iaddr[(LGSPAN-1):0]];\n"
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"\t\t\t\tb_ce <= 1'b1;\n"
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"\t\t\tend else begin\n"
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"\t\t\tend else\n"
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"\t\t\t\t// Just to make debugging easier, let\'s\n"
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"\t\t\t\tb_ce <= 1'b0;\n"
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"\t\t\t\t// clear these registers. That\'ll make\n"
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"\t\t\t\t// the transition easier to watch.\n"
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"\t\t\t\tib_a <= {(2*IWIDTH){1'b0}};\n"
|
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"\t\t\t\tib_b <= {(2*IWIDTH){1'b0}};\n"
|
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"\t\t\t\tib_sync <= 1'b0;\n"
|
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"\t\t\tend\n"
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"\n"
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"\n"
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\t// Next step: recover the outputs from the butterfly\n"
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"\t\t\t// Next step: recover the outputs from the butterfly\n"
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"\t\t\t//\n"
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"\t\t\t//\n"
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"\t\t\tif ((ob_sync||b_started)&&(b_ce))\n"
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"\t\t\tif ((ob_sync||b_started)&&(~oB[LGSPAN]))\n"
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"\t\t\tbegin // A butterfly output is available\n"
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"\t\t\tbegin // A butterfly output is available\n"
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"\t\t\t\tb_started <= 1'b1;\n"
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"\t\t\t\tb_started <= 1'b1;\n"
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"\t\t\t\tomem[oB] <= ob_b;\n"
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"\t\t\t\tomem[oB[(LGSPAN-1):0]] <= ob_b;\n"
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"\t\t\t\toB <= oB+1;\n"
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"\t\t\t\toB <= oB+1;\n"
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"\n"
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"\n"
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"\t\t\t\to_sync <= (ob_sync);\n"
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"\t\t\t\to_sync <= (ob_sync);\n"
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"\t\t\t\to_data <= ob_a;\n"
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"\t\t\t\to_data <= ob_a;\n"
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"\t\t\tend else if (b_started)\n"
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"\t\t\tend else if (b_started)\n"
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"\t\t\tbegin // and keep outputting once you start--at a rate\n"
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"\t\t\tbegin // and keep outputting once you start--at a rate\n"
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"\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
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"\t\t\t// of one guaranteed output per clock that has i_ce set.\n"
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"\t\t\t\to_data <= omem[oB];\n"
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"\t\t\t\to_data <= omem[oB[(LGSPAN-1):0]];\n"
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"\t\t\t\toB <= oB + 1;\n"
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"\t\t\t\toB <= oB + 1;\n"
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"\t\t\t\to_sync <= 1'b0;\n"
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"\t\t\t\to_sync <= 1'b0;\n"
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"\t\t\tend else\n"
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"\t\t\tend else\n"
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"\t\t\t\to_sync <= 1'b0;\n"
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"\t\t\t\to_sync <= 1'b0;\n"
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"\t\tend\n"
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"\t\tend\n"
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"\n", (inv)?"i":"");
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"\n", (inv)?"i":"");
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fprintf(fstage,
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fprintf(fstage,
|
"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
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"\tbutterfly #(.IWIDTH(IWIDTH),.CWIDTH(CWIDTH),.OWIDTH(OWIDTH),\n"
|
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
|
"\t\t\t.MPYDELAY(%d\'d%d),.LGDELAY(LGBDLY),.SHIFT(BFLYSHIFT))\n"
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"\t\tbfly(i_clk, i_rst, (b_ce&i_ce), ib_c,\n"
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"\t\tbfly(i_clk, i_rst, i_ce, ib_c,\n"
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"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
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"\t\t\tib_a, ib_b, ib_sync, ob_a, ob_b, ob_sync);\n"
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"endmodule;\n",
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"endmodule;\n",
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lgdelay(nbits, xtra), (1<xtra)?(nbits+4):(nbits+xtra+3));
|
lgdelay(nbits, xtra), (1<xtra)?(nbits+4):(nbits+xtra+3));
|
}
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}
|
|
|
