| Line 27... |
Line 27... |
* cs#---|___|---------
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* cs#---|___|---------
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*
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*
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* | | |
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* | | |
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* t0 t1 t2 ....
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* t0 t1 t2 ....
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*
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*
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*
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*/
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*/
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module ddr3_simple4#(
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module ddr3_simple4#(
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parameter MEM_DQ_WIDTH =8,
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parameter MEM_DQ_WIDTH =8,
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parameter MEM_BA_WIDTH =3,
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parameter MEM_BA_WIDTH =3,
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parameter MEM_ROW_WIDTH =13,
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parameter MEM_ROW_WIDTH =13,
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parameter MEM_COL_WIDTH =13,
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parameter MEM_COL_WIDTH =13,
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parameter MEM_TRTP =6,
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parameter MEM_AL =0,
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parameter MEM_TRCD =11,
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parameter MEM_CWL =8, //CWL
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parameter MEM_TWL =8,
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parameter MEM_CL =6 //CL
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parameter MEM_TRL =6,
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parameter MEM_ACT_CMD =7 //activates to command
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)(
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)(
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input wire [MEM_ROW_WIDTH-1:0] a,
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input wire [MEM_ROW_WIDTH-1:0] a,
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input wire [ MEM_BA_WIDTH-1:0] ba,
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input wire [ MEM_BA_WIDTH-1:0] ba,
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input wire ck,
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input wire ck,
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input wire ck_n,
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input wire ck_n,
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| Line 59... |
Line 58... |
inout wire dqs,
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inout wire dqs,
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inout wire dqs_n,
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inout wire dqs_n,
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input wire odt
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input wire odt
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);
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);
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//convert actual CL and CWL parameter to
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//definitions
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//definitions
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localparam OPCODE_PRECHARGE = 4'b0010;
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localparam OPCODE_PRECHARGE = 4'b0010;
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localparam OPCODE_ACTIVATE = 4'b0011;
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localparam OPCODE_ACTIVATE = 4'b0011;
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localparam OPCODE_WRITE = 4'b0100;
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localparam OPCODE_WRITE = 4'b0100;
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| Line 71... |
Line 71... |
localparam OPCODE_REFRESH = 4'b0001;
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localparam OPCODE_REFRESH = 4'b0001;
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localparam OPCODE_DES = 4'b1000;
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localparam OPCODE_DES = 4'b1000;
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localparam OPCODE_ZQC = 4'b0110;
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localparam OPCODE_ZQC = 4'b0110;
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localparam OPCODE_NOP = 4'b0111;
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localparam OPCODE_NOP = 4'b0111;
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localparam BL8 = 1'b1;
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localparam BC4 = 1'b0;
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//mode registers
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//mode registers
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reg [31:0] mr0;
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reg [31:0] mr0;
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reg [31:0] mr2;
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reg [31:0] mr2;
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reg [31:0] mr3;
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reg [31:0] mr3;
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| Line 186... |
Line 182... |
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//cmd
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//cmd
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//read
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//read
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ddr3_sr4 #(
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ddr3_sr4 #(
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.PIPE_LEN(MEM_TRL)
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.PIPE_LEN(MEM_CL)
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)ddr3_read_cmd_sr(
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)ddr3_read_cmd_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_read_cmd),
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.shift_in(last_read_cmd),
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.shift_out(read_cmd)
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.shift_out(read_cmd)
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);
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);
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//bank, row, col
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//bank, row, col
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ddr3_sr36 #(
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ddr3_sr36 #(
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.PIPE_LEN(MEM_TRL+1)
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.PIPE_LEN(MEM_CL+1)
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)ddr3_read_add_sr(
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)ddr3_read_add_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_read_add),
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.shift_in(last_read_add),
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.shift_out(read_add)
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.shift_out(read_add)
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);
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);
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//cmd
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//cmd
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//write
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//write
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ddr3_sr4#(
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ddr3_sr4#(
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.PIPE_LEN(MEM_TWL)
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.PIPE_LEN(MEM_CWL)
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)ddr3_write_cmd_sr(
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)ddr3_write_cmd_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_write_cmd),
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.shift_in(last_write_cmd),
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.shift_out(write_cmd)
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.shift_out(write_cmd)
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);
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);
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//bank, row, col
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//bank, row, col
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ddr3_sr36#(
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ddr3_sr36#(
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.PIPE_LEN(MEM_TWL+1) //have to be a cycle late to wait for IDDR latency
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.PIPE_LEN(MEM_CWL+1) //have to be a cycle late to wait for IDDR latency
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) ddr3_write_add_sr(
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) ddr3_write_add_sr(
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.clk(ck),
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.clk(ck),
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.shift_in(last_write_add),
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.shift_in(last_write_add),
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.shift_out(write_add)
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.shift_out(write_add)
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);
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);
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| Line 416... |
Line 412... |
send_dqs0<=send_dqs1;
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send_dqs0<=send_dqs1;
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end//end always
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end//end always
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//ram here
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//ram here
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dport_ram #(
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dport_ram #(
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.DATA_WIDTH(8), //data_hi,data_lo
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.DATA_WIDTH(MEM_DQ_WIDTH), //data_hi,data_lo
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.ADDR_WIDTH(36)
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.ADDR_WIDTH(36)
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)dport_ram_hi(
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)dport_ram_hi(
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.clk (ck),
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.clk (ck),
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.di (data_hi),
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.di (data_hi),
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.read_addr (read_add+read_col),
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.read_addr (read_add+read_col),
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| Line 428... |
Line 424... |
.we (mem_we & data_hi_dm),
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.we (mem_we & data_hi_dm),
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.do (read_data[15:8])
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.do (read_data[15:8])
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);
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);
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dport_ram #(
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dport_ram #(
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.DATA_WIDTH(8), //data_hi,data_lo
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.DATA_WIDTH(MEM_DQ_WIDTH), //data_hi,data_lo
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.ADDR_WIDTH(36)
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.ADDR_WIDTH(36)
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)dport_ram_lo(
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)dport_ram_lo(
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.clk (ck),
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.clk (ck),
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.di (data_lo),
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.di (data_lo),
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.read_addr (read_add+read_col),
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.read_addr (read_add+read_col),
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| Line 444... |
Line 440... |
assign dqs_n=((send_dqs0==1'b1) || (send_dq==1'b1))?ck_n:1'bz;
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assign dqs_n=((send_dqs0==1'b1) || (send_dq==1'b1))?ck_n:1'bz;
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assign dq = (send_dq==1'b1)?dq_out:8'hZZ;
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assign dq = (send_dq==1'b1)?dq_out:8'hZZ;
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/* utility functions to display information
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/* utility functions to display information
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*/
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*/
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initial begin
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initial begin
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$timeformat (-9, 1, " ns", 1);
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$timeformat (-9, 1, " ns", 1);
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end
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end
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always @(posedge ck )
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always @(posedge ck )
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| Line 464... |
Line 461... |
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OPCODE_DES :begin
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OPCODE_DES :begin
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$display("%m: at time %t DES ",$time);
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$display("%m: at time %t DES ",$time);
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end
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end
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OPCODE_MRS :begin
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OPCODE_MRS :begin
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$display("%m: at time %t MRS ",$time);
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$display("%m: at time %t MRS - MR[%d]",$time,ba[1:0]);
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end
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case(ba[1:0])
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2'b00:begin //MR0
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case(a[1:0]) // burst length
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2'b00:$display("%m\tBL = BL8 \(Fixed\)");
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2'b01:$display("%m\tBL = BC4/BL8 OTF");
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2'b10:$display("%m\tBL = BC4 (Fixed)");
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2'b11:$display("%m\tBL = Reserved");
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endcase
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case({a[6:4],a[2]}) //CAS Latency
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4'b0000:$display("%m\tCL = Reserved");
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4'b0010:$display("%m\tCL = 5");
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4'b0100:$display("%m\tCL = 6");
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4'b0110:$display("%m\tCL = 7");
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4'b1000:$display("%m\tCL = 8");
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4'b1010:$display("%m\tCL = 9");
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4'b1100:$display("%m\tCL = 10");
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4'b1111:$display("%m\tCL = 11(Optional for DD3-1600)");
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4'b0001:$display("%m\tCL = 12");
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4'b0011:$display("%m\tCL = 13");
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4'b0101:$display("%m\tCL = 14");
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4'b0111:$display("%m\tCL = Reserved for 15");
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4'b1001:$display("%m\tCL = Reserved for 16");
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4'b1011:$display("%m\tCL = Reserved");
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4'b1101:$display("%m\tCL = Reserved");
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4'b1111:$display("%m\tCL = Reserved");
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endcase
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case(a[11:9]) //Write Recover
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3'b000:$display("%m\tWR = 16^2(256 cycles)");
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3'b001:$display("%m\tWR = 5^2( 25 cycles)");
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3'b010:$display("%m\tWR = 6^2( 36 cycles)");
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3'b011:$display("%m\tWR = 7^2( 49 cycles)");
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3'b100:$display("%m\tWR = 8^2( 64 cycles)");
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3'b101:$display("%m\tWR = 10^2(100 cycles)");
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3'b110:$display("%m\tWR = 12^2(144 cycles)");
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3'b111:$display("%m\tWR = 14^2(196 cycles)");
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endcase
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end//end MR0
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2'b01:begin //MR1
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end//end MR1
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2'b10:begin //MR2
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end//end MR2
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2'b11:begin //MR3
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end//end MR3
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endcase //end which MRS
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end //end MRS
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/*OPCODE_NOP :begin
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/*OPCODE_NOP :begin
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/$display("%m: at time %t WRITE ",$time);
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/$display("%m: at time %t WRITE ",$time);
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end
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end
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*/
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*/
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/*
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/*
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