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https://opencores.org/ocsvn/dds_synthesizer/dds_synthesizer/trunk
[/] [dds_synthesizer/] [trunk/] [vhdl/] [dds_synthesizer.vhd] - Diff between revs 5 and 8
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Rev 5 |
Rev 8 |
Line 87... |
Line 87... |
process (clk_i, rst_i)
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process (clk_i, rst_i)
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begin
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begin
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if rst_i = '1' then
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if rst_i = '1' then
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ftw_accu <= (others => '0');
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ftw_accu <= (others => '0');
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phase <= (others => '0');
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phase <= (others => '0');
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lut_out <= (others => '0');
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lut_out_delay <= (others => '0');
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lut_out_inv_delay <= (others => '0');
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quadrant_3_or_4_delay <= '0';
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quadrant_3_or_4_2delay <= '0';
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elsif clk_i'event and clk_i = '1' then
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elsif clk_i'event and clk_i = '1' then
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ftw_accu <= conv_std_logic_vector(conv_integer(ftw_accu) + conv_integer(ftw_i), ftw_width);
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ftw_accu <= ftw_accu + ftw_i;
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phase <= conv_std_logic_vector(conv_integer(ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH)) + conv_integer(phase_i), PHASE_WIDTH);
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phase <= ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH) + phase_i;
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if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then
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if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then
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lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);
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lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);
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else
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else
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lut_out <= sine_lut(conv_integer(lut_in));
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lut_out <= sine_lut(conv_integer(lut_in));
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end if;
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end if;
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